9DBV0541 Datasheet PDF | IDT





9DBV0541 Datasheet PDF Download

Part Number 9DBV0541
Description 5 Output 1.8V HCSL Fanout Buffer
Manufacture IDT
Total Page 16 Pages
PDF Download Download 9DBV0541 Datasheet PDF

Features: 5 O/P 1.8V PCIe Gen1-2-3 Fan-out Buffer w/Zo=100ohms 9DBV0541 DATASHEET Descr iption The 9DBV0541 is a member of IDT' s 1.8V Very-Low-Power (VLP) PCIe family . It has integrated terminations for di rect connection to 100ohm transmission lines. The device has 5 output enables for clock management, and 3 selectable SMBus addresses. Recommended Applicatio n 1.8V PCIe Gen1-2-3 Fan-out Buffer (FO B) Output Features • 5 – 1-200MHz L ow-Power (LP) HCSL DIF pairs w/Zo=100ï — Key Specifications • DIF additive c ycle-to-cycle jitter <5ps • DIF outpu t-to-output skew < 50ps • DIF additiv e phase jitter is <100fs rms for PCIe G en3 • DIF additive phase jitter <300f s rms for SGMII Features/Benefits • Integrated terminations; save 36 resist ors compared to standard HCSL outputs ⠀¢ 50mW typical power consumption; mini mal power consumption • OE# pins; sup port DIF power management • HCSL comp atible differential input; can be drive n by common clock sources • Programmable Slew rate for each o.

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9DBV0541 datasheet
5 Output 1.8V HCSL Fanout Buffer with
Zo = 100ohms
9DBV0541
DATASHEET
Description
The 9DBV0541 is a member of IDT's Full-Featured PCIe
family. The device has 5 output enables for clock
management, and 3 selectable SMBus addresses. It has
integrated terminations for direct connection to 100ohm
transmission lines.
Recommended Application
PCIe Gen1–3 clock distribution in Storage, Networking,
Computing, Consumer
Output Features
• Five 1–200MHz Low-Power (LP) HCSL DIF pairs with
Zo = 100
• Easy AC-coupling to other logic families, see IDT
application note AN-891
Key Specifications
• Additive cycle-to-cycle jitter < 5ps
• Output-to-output skew < 50ps
• Additive phase jitter is < 100fs rms for PCIe Gen3
• Additive phase jitter < 300fs rms (12kHz–20MHz at
125MHz)
Features/Benefits
• 100 direct connect; saves 20 resistors and 34mm2
compared to standard HCSL
• 50mW typical power consumption; eliminates thermal
concerns
• OE# pins; support DIF power management
• HCSL-compatible differential input; can be driven by
common clock sources
• Spread spectrum compatible; allows EMI reduction
• SMBus-selectable features allow optimization to customer
requirements
• Slew rate for each output; allows tuning for various line
length
• Differential output amplitude; allows tuning for various
application environments
• 1MHz to 200MHz operating frequency
• 3.3V tolerant SMBus interface works with legacy controllers
• Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
• Device contains default configuration; SMBus interface not
required for device operation
• 32-pin 5 x 5 mm QFN; minimal board space
Block Diagram
vOE(4:0)#
CLK_IN
CLK_IN#
vSADR
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
5
CONTROL
LOGIC
DIF4
DIF3
DIF2
DIF1
DIF0
9DBV0541 OCTOBER 27, 2017
1 ©2017 Integrated Device Technology, Inc.

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