9DBV0741 Datasheet: 7-output 1.8V HCSL Fanout Buffer





9DBV0741 7-output 1.8V HCSL Fanout Buffer Datasheet

Part Number 9DBV0741
Description 7-output 1.8V HCSL Fanout Buffer
Manufacture IDT
Total Page 17 Pages
PDF Download Download 9DBV0741 Datasheet PDF

Features: 7-output 1.8V HCSL Fanout Buffer w/Zo=10 0ohms 9DBV0741 DATASHEET Description The 9DBV0741 is a member of IDT's Full- Featured PCIe family. The device has 7 output enables for clock management, an d 3 selectable SMBus addresses. It has integrated terminations for direct conn ection to 100ohm transmission lines. Re commended Application PCIe Gen1-3 clock distribution in Storage, Networking, C ompute, Consumer Output Features • 7 – 1-200MHz Low-Power (LP) HCSL DIF pa irs w/ZO=100 • Easy AC-coupling to other logic families, see IDT applicat ion note AN-891 Key Specifications • Additive cycle-to-cycle jitter <5ps • Output-to-output skew < 60ps • Addit ive phase jitter is <100fs rms for PCIe Gen3 • Additive phase jitter <300fs rms (12kHz-20MHz @125MHz) Block Diagra m vOE(6:0)# 7 CLK_IN CLK_IN# vSADR ^ CKPWRGD_PD# SDATA_3.3 SCLK_3.3 CONTROL LOGIC Features/Benefits • 100ohm di rect connect; saves 28 resistors and 48 mm2 compared to standard HCSL • 41mW typical power consumptio.

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7-Output 1.8V HCSL Fanout Buffer with
Zo=100ohms
9DBV0741
DATASHEET
Description
The 9DBV0741 is a member of IDT's Full-Featured PCIe
family. The device has 7 output enables for clock
management, and 3 selectable SMBus addresses. It has
integrated terminations for direct connection to 100
transmission lines.
Recommended Application
PCIe Gen1–3 clock distribution in Storage, Networking,
Compute, Consumer
Output Features
7 1–200MHz Low-Power (LP) HCSL DIF pairs with
ZO=100
Easy AC-coupling to other logic families, see IDT
application note AN-891
Key Specifications
Additive cycle-to-cycle jitter < 5ps
Output-to-output skew < 60ps
Additive phase jitter is < 100fs rms for PCIe Gen3
Additive phase jitter < 300fs rms (12kHz–20MHz at
125MHz)
Block Diagram
vOE(6:0)#
7
CLK_IN
CLK_IN#
vSADR
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
Features/Benefits
100direct connect; saves 28 resistors and 48mm2
compared to standard HCSL
41mW typical power consumption; eliminates thermal
concerns
Outputs can optionally be supplied from any voltage
between 1.05V and 1.8V; maximum power savings
OE# pins; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
SMBus-selectable features allow optimization to customer
requirements
Slew rate for each output; allows tuning for various line
lengths
Differential output amplitude; allows tuning for various
application environments
1MHz to 200MHz operating frequency
3.3V tolerant SMBus interface works with legacy controllers
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
Device contains default configuration; SMBus interface not
required for device operation
40-pin 5 x 5 mm VFQFPN; minimal board space
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9DBV0741 MARCH 10, 2017
1 ©2017 Integrated Device Technology, Inc.

                    
                    






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