9DBV0841 Datasheet: 8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER





9DBV0841 8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER Datasheet

Part Number 9DBV0841
Description 8-OUTPUT VERY LOW POWER PCIE GEN1-2-3 BUFFER
Manufacture IDT
Total Page 16 Pages
PDF Download Download 9DBV0841 Datasheet PDF

Features: 8-output 1.8V PCIe Gen1-3 Zero-Delay/Fan -out Buffer w/Zo=100ohms 9DBV0841 DATA SHEET Description The 9DBV0841 is a 1. 8V member of IDT's full featured PCIe f amily. It has integrated output termina tions providing Zo=100 for direct co nnection for 100 transmission lines. The device has 8 output enables for cl ock management and 3 selectable SMBus a ddresses. Recommended Application SSD, microServers, WLAN Access points Output Features • 8 – 1-200Hz Low-Power ( LP) HCSL DIF pairs Key Specifications DIF cycle-to-cycle jitter <50ps • DIF output-to-output skew <50ps • DIF additive phase jitter is <100fs rms fo r PCIe Gen3 • DIF additive phase jitt er <300fs rms for 12k-20MHz Block Diagr am Features/Benefits • LP-HCSL outpu ts save 32 resistors; minimal board spa ce and BOM cost • 62mW typical power consumption in PLL mode; eliminates the rmal concerns • Spread Spectrum (SS) compatible; allows use of SS for EMI re duction • OE# pins; support DIF power management • HCSL com.

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8-output 1.8V PCIe Gen1-3
Zero-Delay/Fan-out Buffer w/Zo=100ohms
9DBV0841
DATASHEET
Description
The 9DBV0841 is a 1.8V member of IDT's full featured PCIe
family. It has integrated output terminations providing
Zo=100for direct connection for 100transmission lines.
The device has 8 output enables for clock management and 3
selectable SMBus addresses.
Recommended Application
SSD, microServers, WLAN Access points
Output Features
8 – 1-200Hz Low-Power (LP) HCSL DIF pairs
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF additive phase jitter is <100fs rms for PCIe Gen3
DIF additive phase jitter <300fs rms for 12k-20MHz
Block Diagram
Features/Benefits
LP-HCSL outputs save 32 resistors; minimal board space
and BOM cost
62mW typical power consumption in PLL mode; eliminates
thermal concerns
Spread Spectrum (SS) compatible; allows use of SS for
EMI reduction
OE# pins; support DIF power management
HCSL compatible differential input; can be driven by
common clock sources
Programmable Slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
Pin/software selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
Outputs blocked until PLL is locked; clean system start-up
Software selectable 50MHz or 125MHz PLL operation;
useful for Ethernet applications
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacy controllers
Space saving 48-pin 6x6mm VFQFPN; minimal board
space
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
vOE(7:0)#
8
CLK_IN
CLK_IN#
vSADR
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
Control
Logic
SS
Compatible
PLL
DIF7
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9DBV0841 APRIL 28, 2016
1 ©2016 Integrated Device Technology, Inc.

                    
                    






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