9DBL06

6-output 3.3V PCIe Zero-Delay Buffer 9DBL06 Description The 9DBL06 devices are 3.3V members of IDT's Full-Featured PCIe family. The 9DBL06 supports PCIe Gen1-4 Common Clocked (CC) and PCIe Separate Reference Independent Spread (SRIS) systems. It offers a choice of integrated output terminations providing direct connection to 85Ω or 100Ω transmission lines. The 9DBL06P1 can be factory programmed with a user-defined power up default SMBus configuration. Recommended Application PCIe Gen1-4 clock distribution for Riser Cards, Storage, Networking, JBOD, Communications, Access Points Output Features 6 – 1-200 MHz Low-Power (LP) HCSL DIF pairs 9DBL0641 default ZOUT = 100 9DBL0651 default ZOUT = 85 9DBL06P1 factory programmable defaults Key Specifications PCIe Gen1-2-3-4 CC compliant in ZDB mode PCIe Gen2 SRIS compliant in ZDB mode Supports PCIe Gen2-3 SRIS in fan-out mode DIF cycle-to-cycle jitter <50ps DIF output-to-output skew < 50ps Byp...