9DBV0431 Datasheet: 4-output 1.8V PCIe Gen1-2-3 Zero-delay/Fanout Buffer





9DBV0431 4-output 1.8V PCIe Gen1-2-3 Zero-delay/Fanout Buffer Datasheet

Part Number 9DBV0431
Description 4-output 1.8V PCIe Gen1-2-3 Zero-delay/Fanout Buffer
Manufacture IDT
Total Page 16 Pages
PDF Download Download 9DBV0431 Datasheet PDF

Features: 4-output 1.8V PCIe Gen1-2-3 Zero-delay/F anout Buffer (ZDB/FOB) 9DBV0431 DATASH EET Description The 9DBV0431 is a memb er of IDT's SOC-Friendly 1.8V Very-Low- Power (VLP) PCIe family. It can also be used for 50M or 125M Ethernet Applicat ions via software frequency selection. The device has 4 output enables for clo ck management, and 3 selectable SMBus a ddresses. Recommended Application 1.8V PCIe Gen1-2-3 Zero-Delay/Fan-out Buffer (ZDB/FOB) Output Features • 4 - 1-20 0Hz Low-Power (LP) HCSL DIF pairs w/ZO= 100ohms Key Specifications • DIF cycl e-to-cycle jitter <50ps • DIF output- to-output skew <50ps • DIF additive p hase jitter is <100fs rms for PCIe Gen3 • DIF additive phase jitter <300fs r ms for 12k-20MHz Block Diagram Feature s/Benefits • LP-HCSL outputs save 8 r esistors; minimal board space and BOM c ost • 53mW typical power consumption in PLL mode; minimal power consumption • OE# pins; support DIF power managem ent • HCSL compatible differential input; can be driven by co.

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4-output 1.8V PCIe Gen1-2-3
Zero-delay/Fanout Buffer (ZDB/FOB)
9DBV0431
DATASHEET
Description
The 9DBV0431 is a member of IDT's SOC-Friendly 1.8V
Very-Low-Power (VLP) PCIe family. It can also be used for
50M or 125M Ethernet Applications via software frequency
selection. The device has 4 output enables for clock
management, and 3 selectable SMBus addresses.
Recommended Application
1.8V PCIe Gen1-2-3 Zero-Delay/Fan-out Buffer (ZDB/FOB)
Output Features
4 - 1-200Hz Low-Power (LP) HCSL DIF pairs
w/ZO=100ohms
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF additive phase jitter is <100fs rms for PCIe Gen3
DIF additive phase jitter <300fs rms for 12k-20MHz
Block Diagram
Features/Benefits
LP-HCSL outputs save 8 resistors; minimal board space
and BOM cost
53mW typical power consumption in PLL mode; minimal
power consumption
OE# pins; support DIF power management
HCSL compatible differential input; can be driven by
common clock sources
Programmable Slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
Pin/software selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
Outputs blocked until PLL is locked; clean system start-up
Software selectable 50MHz or 125MHz PLL operation;
useful for Ethernet applications
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacy controllers
Space saving 32-pin 5x5mm VFQFPN; minimal board
space
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
vOE(3:0)#
4
CLK_IN
CLK_IN#
vSADR
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
SS-
Compatible
PLL
CONTROL
LOGIC
DIF3
DIF2
DIF1
DIF0
9DBV0431 REVISION E 04/28/16 1 ©2016 Integrated Device Technology, Inc.

                    
                    






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