9DBV0441 Datasheet: 4 O/P 1.8V PCIe Gen1-2-3 ZDB/FOB





9DBV0441 4 O/P 1.8V PCIe Gen1-2-3 ZDB/FOB Datasheet

Part Number 9DBV0441
Description 4 O/P 1.8V PCIe Gen1-2-3 ZDB/FOB
Manufacture IDT
Total Page 17 Pages
PDF Download Download 9DBV0441 Datasheet PDF

Features: 4 O/P 1.8V PCIe Gen1-2-3 ZDB/FOB w/Zo=10 0ohm 9DBV0441 DATASHEET Description T he 9DBV0441 is a member of IDT's SOC-Fr iendly 1.8V Very-Low-Power (VLP) PCIe f amily. It has integrated output termina tions providing Zo=100ohms for direct c onnection to 100ohm transmission lines. The device has 4 output enables for cl ock management, and 3 selectable SMBus addresses. Recommended Application 1.8V PCIe Gen1-2-3 Zero-Delay/Fan-out Buffe r (ZDB/FOB) Output Features • 4 – 1 -200Hz Low-Power (LP) HCSL DIF pairs w/ ZO=100 Key Specifications • DIF cy cle-to-cycle jitter <50ps • DIF outpu t-to-output skew <50ps • DIF additive phase jitter is <100fs rms for PCIe Ge n3 • DIF additive phase jitter <300fs rms for 12kHz-20MHz Block Diagram Fea tures/Benefits • Direct connection to 100ohm transmission lines; saves 16 re sistors compared to standard HCSL outpu ts • 53mW typical power consumption i n PLL mode; minimal power consumption Spread Spectrum (SS) compatible; allows use of SS for EMI re.

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4 O/P 1.8V PCIe Gen1-2-3 ZDB/FOB
w/Zo=100ohm
9DBV0441
DATASHEET
Description
The 9DBV0441 is a member of IDT's SOC-Friendly 1.8V
Very-Low-Power (VLP) PCIe family. It has integrated output
terminations providing Zo=100ohms for direct connection to
100ohm transmission lines. The device has 4 output enables
for clock management, and 3 selectable SMBus addresses.
Recommended Application
1.8V PCIe Gen1-2-3 Zero-Delay/Fan-out Buffer (ZDB/FOB)
Output Features
4 – 1-200Hz Low-Power (LP) HCSL DIF pairs w/ZO=100
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF additive phase jitter is <100fs rms for PCIe Gen3
DIF additive phase jitter <300fs rms for 12kHz-20MHz
Block Diagram
Features/Benefits
Direct connection to 100ohm transmission lines; saves 16
resistors compared to standard HCSL outputs
53mW typical power consumption in PLL mode; minimal
power consumption
Spread Spectrum (SS) compatible; allows use of SS for
EMI reduction
OE# pins; support DIF power management
HCSL compatible differential input; can be driven by
common clock sources
Programmable Slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
Pin/software selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
Outputs blocked until PLL is locked; clean system start-up
Software selectable 50MHz or 125MHz PLL operation;
useful for Ethernet applications
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacy controllers
Space saving 32-pin 5x5mm VFQFPN; minimal board
space
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
vOE(3:0)#
CLK_IN
CLK_IN#
^SADR_tri
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
ZDB PLL
DIF3
DIF2
DIF1
DIF0
9DBV0441 REVISION E 04/28/16 1 ©2016 Integrated Device Technology, Inc.

                    
                    






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