9DMU0131 Datasheet | 2:1 1.5V PCIe Gen1-2-3 Clock Mux





(Datasheet) 9DMU0131 Datasheet PDF Download

Part Number 9DMU0131
Description 2:1 1.5V PCIe Gen1-2-3 Clock Mux
Manufacture IDT
Total Page 10 Pages
PDF Download Download 9DMU0131 Datasheet PDF

Features: 2:1 1.5V PCIe Gen1-2-3 Clock Mux 9DMU01 31 DATASHEET General Description The 9DMU0131 is a member of IDT's SOC-Frien dly 1.5V Ultra-Low-Power (ULP) PCIe Gen 1-2-3 family. The output has an OE# pin for optimal system control and power m anagement. The part provides asynchrono us or glitch-free switching modes. Reco mmended Application 2:1 1.5V PCIe Gen1- 2-3 Clock Mux Output Features • 1 – Low-Power (LP) HCSL DIF pair Key Speci fications • DIF additive cycle-to-cyc le jitter <5ps • DIF phase jitter is PCIe Gen1-2-3 compliant • 125MHz addi tive phase jitter 535fs rms typical (12 kHz to 20MHz) Features/Benefits • LP -HCSL output; saves 2 resistors compare d to standard HCSL output • 1.5V oper ation; 11mW typical power consumption Selectable asynchronous or glitch-fr ee switching; allows the mux to be sele cted at power up even if both inputs ar e not running, then transition to glitc h-free switching mode • Spread Spectr um Compatible; supports EMI reduction • OE# pin; supports DIF.

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2:1 1.5V PCIe Gen1-2-3 Clock Mux
9DMU0131
DATASHEET
General Description
The 9DMU0131 is a member of IDT's SOC-Friendly 1.5V
Ultra-Low-Power (ULP) PCIe Gen1-2-3 family. The output
has an OE# pin for optimal system control and power
management. The part provides asynchronous or glitch-free
switching modes.
Recommended Application
2:1 1.5V PCIe Gen1-2-3 Clock Mux
Output Features
1 – Low-Power (LP) HCSL DIF pair
Key Specifications
DIF additive cycle-to-cycle jitter <5ps
DIF phase jitter is PCIe Gen1-2-3 compliant
125MHz additive phase jitter 535fs rms typical (12kHz to
20MHz)
Features/Benefits
LP-HCSL output; saves 2 resistors compared to standard
HCSL output
1.5V operation; 11mW typical power consumption
Selectable asynchronous or glitch-free switching; allows
the mux to be selected at power up even if both inputs are
not running, then transition to glitch-free switching mode
Spread Spectrum Compatible; supports EMI reduction
OE# pin; supports DIF power management
HCSL differential inputs; can be driven by common clock
sources
1MHz to 167MHz operating frequency
Space saving 16-pin 3x3mm VFQFPN; minimal board
space
Block Diagram
^OE0#
DIF_INA
DIF_INB
vSW_MODE
^SEL_A_B#
A
DIF0
B
9DMU0131 REVISION A 09/30/14
1
©2014 Integrated Device Technology, Inc.

                    
        






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