9DMU0431 Datasheet: 2:4 1.5V PCIe Gen1-2-3 Clock Mux





9DMU0431 2:4 1.5V PCIe Gen1-2-3 Clock Mux Datasheet

Part Number 9DMU0431
Description 2:4 1.5V PCIe Gen1-2-3 Clock Mux
Manufacture IDT
Total Page 11 Pages
PDF Download Download 9DMU0431 Datasheet PDF

Features: 2:4 1.5V PCIe Gen1-2-3 Clock Mux 9DMU04 31 DATASHEET General Description The 9DMU0431 is a member of IDT's SOC-Frien dly 1.5V Ultra-Low-Power (ULP) PCIe Gen 1-2-3 family. Each of the 4 outputs has its own dedicated OE# pin for optimal system control and power management. Th e part provides asynchronous and glitch -free switching modes. Recommended Appl ication 2:4 PCIe Gen1-2-3 clock multipl exer Output Features • 4 – Low-Powe r (LP) HCSL DIF pair Key Specifications • DIF additive cycle-to-cycle jitter <5ps • DIF phase jitter is PCIe Gen1 -2-3 compliant • Additive phase jitte r @ 125MHz: 535fs rms typical (12kHz to 20MHz) • DIF output-to-output skew < 50ps Features/Benefits • LP-HCSL out puts; save 8 resistors compared to stan dard HCSL outputs • 1.5V operation; 3 1mW typical power consumption • Selec table asynchronous or glitch-free switc hing; allows the mux to be selected at power up even if both inputs are not ru nning, then transition to glitch-free switching mode • Spread.

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2:4 1.5V PCIe Gen1-2-3 Clock Mux
9DMU0431
DATASHEET
General Description
The 9DMU0431 is a member of IDT's SOC-Friendly 1.5V
Ultra-Low-Power (ULP) PCIe Gen1-2-3 family. Each of the 4
outputs has its own dedicated OE# pin for optimal system
control and power management. The part provides
asynchronous and glitch-free switching modes.
Recommended Application
2:4 PCIe Gen1-2-3 clock multiplexer
Output Features
4 – Low-Power (LP) HCSL DIF pair
Key Specifications
DIF additive cycle-to-cycle jitter <5ps
DIF phase jitter is PCIe Gen1-2-3 compliant
Additive phase jitter @ 125MHz: 535fs rms typical (12kHz
to 20MHz)
DIF output-to-output skew <50ps
Features/Benefits
LP-HCSL outputs; save 8 resistors compared to standard
HCSL outputs
1.5V operation; 31mW typical power consumption
Selectable asynchronous or glitch-free switching; allows
the mux to be selected at power up even if both inputs are
not running, then transition to glitch-free switching mode
Spread Spectrum Compatible; supports EMI reduction
OE# pins; support DIF power management
HCSL differential inputs; can be driven by common clock
sources
1MHz to 167MHz operating frequency
Space saving 24-pin 4x4mm VFQFPN; minimal board
space
Block Diagram
^OE(3:0)#
DIF_INA
DIF_INB
vSW_MODE
^SEL_A_B#
4
,
A
B
DIF3
DIF2
DIF1
DIF0
9DMU0431 REVISION A 09/24/14
1
©2014 Integrated Device Technology, Inc.

                    
           






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