9DMV0141 Datasheet: 2:1 1.8V PCIe Gen1-2-3 Clock Mux





9DMV0141 2:1 1.8V PCIe Gen1-2-3 Clock Mux Datasheet

Part Number 9DMV0141
Description 2:1 1.8V PCIe Gen1-2-3 Clock Mux
Manufacture IDT
Total Page 12 Pages
PDF Download Download 9DMV0141 Datasheet PDF

Features: 2:1 1.8V PCIe Gen1-2-3 Clock Mux w/Zo=10 0ohms 9DMV0141 DATASHEET General Desc ription The 9DMV0141 is a member of IDT 's SOC-Friendly 1.8V Very-Low-Power (VL P) PCIe Gen1-2-3 family. It has integra ted output terminations providing Zo=10 0 for direct connection to 100 tr ansmission lines. The output has an OE# pin for optimal system control and pow er management. The part provides asynch ronous or glitch-free switching modes. Recommended Application 2:1 PCIe Gen1-2 -3 Clock Multiplexer Output Features 1 -Low-Power (LP) HCSL DIF pair w/ZO= 100 Key Specifications • DIF addit ive cycle-to-cycle jitter <5ps • DIF phase jitter is PCIe Gen1-2-3 compliant • 125MHz additive phase jitter 420fs rms typical (12kHz to 20MHz) Block Dia gram ^OE0# Features/Benefits • LP-HC SL output w/integrated terminations; sa ves 4 resistors compared to standard HC SL output • 1.8V operation; 12mW typi cal power consumption • Selectable as ynchronous or glitch-free switching; allows the mux to be selec.

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2:1 1.8V PCIe Gen1-2-3 Clock Mux with
Zo=100ohms
9DMV0141
DATASHEET
Description
The 9DMV0141 is a member of IDT's SOC-Friendly 1.8V
Very-Low-Power (VLP) PCIe Gen1-2-3 family. It has
integrated output terminations providing Zo=100for direct
connection to 100transmission lines. The output has an
OE# pin for optimal system control and power management.
The part provides asynchronous or glitch-free switching
modes.
Typical Application
2:1 PCIe Gen1-2-3 Clock Multiplexer
Output Features
1 -Low-Power (LP) HCSL DIF pair w/ZO=100
Key Specifications
DIF additive cycle-to-cycle jitter <5ps
DIF phase jitter is PCIe Gen1-2-3 compliant
125MHz additive phase jitter 420fs rms typical (12kHz to
20MHz)
Block Diagram
^OE0#
Features
LP-HCSL output w/integrated terminations; saves 4
resistors compared to standard HCSL output
1.8V operation; 12mW typical power consumption
Selectable asynchronous or glitch-free switching; allows
the mux to be selected at power up even if both inputs are
not running, then transition to glitch-free switching mode
Spread Spectrum Compatible; supports EMI reduction
OE# pins; support DIF power management
HCSL differential inputs; can be driven by common clock
sources
1MHz to 200MHz operating frequency
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
Space saving 16-pin 3x3mm VFQFPN; minimal board
space
DIF_INA
DIF_INB
vSW_MODE
^SEL_A_B#
A
DIF0
B
9DMV0141 AUGUST 15, 2017
1 ©2017 Integrated Device Technology, Inc.

                    
              






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