9DMV0441 Datasheet: 2:4 1.8V PCIe Gen1-2-3 Clock Mux





9DMV0441 2:4 1.8V PCIe Gen1-2-3 Clock Mux Datasheet

Part Number 9DMV0441
Description 2:4 1.8V PCIe Gen1-2-3 Clock Mux
Manufacture IDT
Total Page 12 Pages
PDF Download Download 9DMV0441 Datasheet PDF

Features: 2:4 1.8V PCIe Gen1-2-3 Clock Mux w/Zo=10 0ohms 9DMV0441 DATASHEET General Desc ription The 9DMV0441 is a member of IDT 's SOC-Friendly 1.8V Very-Low-Power (VL P) PCIe Gen1-2-3 family. It has integra ted output terminations providing Zo=10 0 for direct connection to 100 tr ansmission lines. Each of the 4 outputs has its own dedicated OE# pin for opti mal system control and power management . The part provides asynchronous and gl itch-free switching modes. Recommended Application 2:4 PCIe Gen1-2-3 Clock Mul tiplexer Output Features • 4 -Low-Pow er (LP) HCSL DIF pairs w/ZO=100 Key Specifications • DIF additive cycle-t o-cycle jitter <5ps • DIF phase jitte r is PCIe Gen1-2-3 compliant • Additi ve phase jitter @ 125MHz: 420fs rms typ ical (12kHz to 20MHz) • DIF output-to -output skew <50ps Features/Benefits LP-HCSL outputs w/integrated termina tions; saves 16 resistors compared to s tandard HCSL outputs • 1.8V operation ; 36mW typical power consumption • Selectable asynchronous or.

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2:4 1.8V PCIe Gen1-2-3 Clock Mux
w/Zo=100ohms
9DMV0441
DATASHEET
General Description
The 9DMV0441 is a member of IDT's SOC-Friendly 1.8V
Very-Low-Power (VLP) PCIe Gen1-2-3 family. It has
integrated output terminations providing Zo=100for direct
connection to 100transmission lines. Each of the 4 outputs
has its own dedicated OE# pin for optimal system control and
power management. The part provides asynchronous and
glitch-free switching modes.
Recommended Application
2:4 PCIe Gen1-2-3 Clock Multiplexer
Output Features
4 -Low-Power (LP) HCSL DIF pairs w/ZO=100
Key Specifications
DIF additive cycle-to-cycle jitter <5ps
DIF phase jitter is PCIe Gen1-2-3 compliant
Additive phase jitter @ 125MHz: 420fs rms typical (12kHz
to 20MHz)
DIF output-to-output skew <50ps
Features/Benefits
LP-HCSL outputs w/integrated terminations; saves 16
resistors compared to standard HCSL outputs
1.8V operation; 36mW typical power consumption
Selectable asynchronous or glitch-free switching; allows
the mux to be selected at power up even if both inputs are
not running, then transition to glitch-free switching mode
Spread Spectrum Compatible; supports EMI reduction
OE# pins; support DIF power management
HCSL differential inputs; can be driven by common clock
sources
1MHz to 200MHz operating frequency
Space saving 24-pin 4x4mm VFQFPN; minimal board
space
Block Diagram
^OE(3:0)#
DIF_INA
DIF_INB
vSW_MODE
^SEL_A_B#
4
,
A
B
DIF3
DIF2
DIF1
DIF0
9DMV0441 REVISION B 01/26/15
1
©2015 Integrated Device Technology, Inc.

                    
              






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