9ZX21201 Datasheet PDF Download, IDT





(PDF) 9ZX21201 Datasheet Download

Part Number 9ZX21201
Description 12-OUTPUT DIFFERENTIAL Z-BUFFER
Manufacture IDT
Total Page 16 Pages
PDF Download Download 9ZX21201 Datasheet PDF

Features: DATASHEET 12-OUTPUT DIFFERENTIAL Z-BUFF ER FOR PCIE GEN2/3 AND QPI 9ZX21201 Ge neral Description The IDT9ZX21201 is a 12-output DB1200Z suitable for PCI-Expr ess Gen3 or QPI applications. The part is backwards compatible to PCIe Gen1 an d Gen2. A fixed external feedback maint ains low drift for critical QPI applica tions. In bypass mode, the IDT9ZX21201 can provide outputs up to 150MHz. Recom mended Application 12-output PCIe Gen3/ QPI differential buffer for Romley and newer platforms Key Specifications • Cycle-to-cycle jitter <50ps • Output -to-output skew < 65 ps • Input-to-ou tput delay variation <50ps • PCIe Gen 3 phase jitter < 1.0ps RMS • QPI 9.6G T/s 12UI phase jitter < 0.2ps RMS Feat ures/Benefits • Space-saving 64-pin p ackages • Fixed feedback path/ 0ps in put-to-output delay • 9 Selectable SM Bus Addresses/Mulitple devices can shar e the same SMBus Segment • 12 OE# pin s/Hardware control of each output • P LL or bypass mode/PLL can dejitter incoming clock • 100MHz or.

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DATASHEET
12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN2/3 AND QPI 9ZX21201
General Description
The IDT9ZX21201 is a 12-output DB1200Z suitable for PCI-Express
Gen3 or QPI applications. The part is backwards compatible to
PCIe Gen1 and Gen2. A fixed external feedback maintains low drift
for critical QPI applications. In bypass mode, the IDT9ZX21201 can
provide outputs up to 150MHz.
Recommended Application
12-output PCIe Gen3/ QPI differential buffer for Romley and newer
platforms
Key Specifications
• Cycle-to-cycle jitter <50ps
• Output-to-output skew < 65 ps
• Input-to-output delay variation <50ps
• PCIe Gen3 phase jitter < 1.0ps RMS
• QPI 9.6GT/s 12UI phase jitter < 0.2ps RMS
Features/Benefits
• Space-saving 64-pin packages
• Fixed feedback path/ 0ps input-to-output delay
• 9 Selectable SMBus Addresses/Mulitple devices can share
the same SMBus Segment
• 12 OE# pins/Hardware control of each output
• PLL or bypass mode/PLL can dejitter incoming clock
• 100MHz or 133MHz PLL mode operation/supports PCIe
and QPI applications
• Selectable PLL bandwidth/minimizes jitter peaking in
downstream PLL's
• Spread Spectrum Compatible/tracks spreading input clock
for low EMI
• Software control of PLL Bandwidth and Bypass Settings/
PLL can dejitter incoming clock (B Rev only)
Output Features
• 12 - 0.7V differential HCSL output pairs
Functional Block Diagram
OE(11:0)#
DIF_IN
DIF_IN#
HIBW_BYPM_LOBW#
100M_133M#
CKPWRGD/PD#
SMB_A0_tri
SMB_A1_tri
SMBDAT
SMBCLK
Logic
Z-PLL
(SS Compatible)
DFB_OUT
DIF(11:0)
Note: Even though the feedback is fixed, DFB_OUT still needs a
termination network for the part to function.
IDT® 12-Output Differential Z-buffer for PCIe Gen2/3 and QPI
1
IREF
1682D - 11/19/15

                    
                    






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