9ZXL1231 Data Sheet PDF | IDT





(Datasheet) 9ZXL1231 PDF Download

Part Number 9ZXL1231
Description 12-output DB1200ZL
Manufacture IDT
Total Page 18 Pages
PDF Download Download 9ZXL1231 Datasheet PDF

Features: 12-output DB1200ZL 9ZXL1231 DATASHEET General Description The 9ZXL1231 meets the demanding requirements of the Inte l DB1200ZL specification, including the critical low-drift requirements of Int el CPUs. Recommended Application Buffer for Romley, Grantley and Purley Server s, solid state storage and PCIe Output Features • 12 - Low-Power (LP) HCSL o utput pairs Key Specifications • Cycl e-to-cycle jitter <50ps • Output-to-o utput skew <50 ps • Input-to-output d elay variation <50ps • PCIe Gen3 phas e jitter <1.0ps RMS • Phase jitter: Q PI/UPI >=9.6GB/s <0.2ps rms Block Diagr am OE(11:0)# Features/Benefits • Low -power push-pull HCSL outputs; eliminat e 24 resistors, save 41mm2 of area • Pin compatible to 9ZX21201; easy path t o >50% power savings • Space-saving 6 4 VFQFPN package • Fixed feedback pat h for 0ps input-to-output delay • 9 S electable SMBus Addresses; multiple dev ices can share the same SMBus Segment 12 OE# pins; hardware control of each output • PLL or bypa.

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9ZXL1231 datasheet
12-output DB1200ZL
9ZXL1231
DATASHEET
General Description
The 9ZXL1231 meets the demanding requirements of the
Intel DB1200ZL specification, including the critical low-drift
requirements of Intel CPUs.
Recommended Application
Buffer for Romley, Grantley and Purley Servers, solid state
storage and PCIe
Output Features
12 - Low-Power (LP) HCSL output pairs
Key Specifications
Cycle-to-cycle jitter <50ps
Output-to-output skew <50 ps
Input-to-output delay variation <50ps
PCIe Gen3 phase jitter <1.0ps RMS
Phase jitter: QPI/UPI >=9.6GB/s <0.2ps rms
Block Diagram
OE(11:0)#
Features/Benefits
Low-power push-pull HCSL outputs; eliminate 24 resistors,
save 41mm2 of area
Pin compatible to 9ZX21201; easy path to >50% power
savings
Space-saving 64 VFQFPN package
Fixed feedback path for 0ps input-to-output delay
9 Selectable SMBus Addresses; multiple devices can
share the same SMBus Segment
12 OE# pins; hardware control of each output
PLL or bypass mode; PLL can dejitter incoming clock
Selectable PLL bandwidth; minimizes jitter peaking in
downstream PLL's
Spread Spectrum Compatible; tracks spreading input clock
for low EMI
DIF_IN
DIF_IN#
Z-PLL
(SS Compatible)
DFB_OUT_NC
DIF(11:0)
HIBW_BYPM_LOBW#
100M_133M#
CKPWRGD/PD#
SMB_A0_tri
SMB_A1_tri
SMBDAT
SMBCLK
Logic
9ZXL1231 REVISION J 05/25/16
1 ©2016 Integrated Device Technology, Inc.

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