9ZXL1251 Datasheet: 12-output DB1200ZL Derivative





9ZXL1251 12-output DB1200ZL Derivative Datasheet

Part Number 9ZXL1251
Description 12-output DB1200ZL Derivative
Manufacture IDT
Total Page 20 Pages
PDF Download Download 9ZXL1251 Datasheet PDF

Features: 12-output DB1200ZL Derivative with Integ rated 85Ω Terminations 9ZXL1251 DATA SHEET General Description The 9ZXL1251 meets the demanding requirements of th e Intel DB1200ZL specification, includi ng the critical low-drift requirements of Intel CPUs. It is pin compatible to the 9ZXL1231 and integrates 24 terminat ion resistors, saving 41mm2 board area. Recommended Application Buffer for Rom ley, Grantley and Purley Servers, solid state storage and PCIe Output Features • 12 LP-HCSL Output Pairs w/integrat ed terminations (Zo = 85Ω) Key Specif ications • Cycle-to-cycle jitter <50p s • Output-to-output skew <50ps • I nput-to-output delay variation <50ps PCIe Gen3 phase jitter <1.0ps RMS • Phase jitter: QPI/UPI >=9.6GB/s <0.2ps rms Features/Benefits • 85Ω Low-p ower push-pull HCSL outputs; eliminate 24 resistors, save 41mm2 of area • Pi n compatible to 9ZX21201 and 9ZXL1231; easy path to power and area savings • Space-saving 64-pin VFQFPN package • Fixed feedback path for.

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12-output DB1200ZL Derivative with
Integrated 85Terminations
9ZXL1251
DATASHEET
General Description
The 9ZXL1251 meets the demanding requirements of the
Intel DB1200ZL specification, including the critical low-drift
requirements of Intel CPUs. It is pin compatible to the
9ZXL1231 and integrates 24 termination resistors, saving
41mm2 board area.
Recommended Application
Buffer for Romley, Grantley and Purley Servers, solid state
storage and PCIe
Output Features
12 LP-HCSL Output Pairs w/integrated terminations (Zo =
85)
Key Specifications
Cycle-to-cycle jitter <50ps
Output-to-output skew <50ps
Input-to-output delay variation <50ps
PCIe Gen3 phase jitter <1.0ps RMS
Phase jitter: QPI/UPI >=9.6GB/s <0.2ps rms
Features/Benefits
85Low-power push-pull HCSL outputs; eliminate 24
resistors, save 41mm2 of area
Pin compatible to 9ZX21201 and 9ZXL1231; easy path to
power and area savings
Space-saving 64-pin VFQFPN package
Fixed feedback path for 0ps input-to-output delay
9 Selectable SMBus Addresses; multiple devices can
share the same SMBus Segment
12 OE# pins; hardware control of each output
PLL or bypass mode; supports common and separate clock
architectures
Selectable PLL bandwidth; minimizes jitter peaking in
downstream PLL's
Spread Spectrum Compatible; tracks spreading input clock
for low EMI
-40°C to +85°C device available; supports demanding
environmental applications
Block Diagram
OE(11:0)#
DIF_IN
DIF_IN#
Z-PLL
(SS Compatible)
DFB_OUT_NC
DIF(11:0)
HIBW_BYPM_LOBW#
100M_133M#
CKPWRGD/PD#
SMB_A0_tri
SMB_A1_tri
SMBDAT
SMBCLK
Logic
9ZXL1251 REVISION B 11/20/15 1 ©2015 Integrated Device Technology, Inc.

                    
                    






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