9ZXL1550 Datasheet: 15-output DB1900Z Low-Power Derivative





9ZXL1550 15-output DB1900Z Low-Power Derivative Datasheet

Part Number 9ZXL1550
Description 15-output DB1900Z Low-Power Derivative
Manufacture IDT
Total Page 18 Pages
PDF Download Download 9ZXL1550 Datasheet PDF

Features: 15-output DB1900Z Low-Power Derivative 9ZXL1550 DATASHEET Description The 9Z XL1550 is a DB1900Z derivative buffer u tilizing Low-Power HCSL (LP-HCSL) outpu ts to increase edge rates on long trace s, reduce board space, and reduce power consumption more than 50% from the ori ginal 9ZX21501. It is pin-compatible to the 9ZXL1530 and has the output termin ations integrated. It is suitable for P CI-Express Gen1/2/3 or QPI/UPI applicat ions, and uses a fixed external feedbac k to maintain low drift for demanding Q PI/UPI applications. Recommended Applic ation Buffer for Romley, Grantley and P urley Servers Key Specifications • Cy cle-to-cycle jitter: < 50ps • Output- to-output skew: <75ps • Input-to-outp ut delay variation: <50ps • Phase jit ter: PCIe Gen3 < 1ps rms • Phase jitt er: QPI 9.6GB/s < 0.2ps rms Block Diagr am Features/Benefits • LP-HCSL outpu ts; up to 90% IO power reduction, bette r signal integrity over long traces • Direct connect to 85Ω transmission lines; eliminates 60 term.

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15-output DB1900Z Low-Power Derivative
9ZXL1550
DATASHEET
Description
The 9ZXL1550 is a DB1900Z derivative buffer utilizing
Low-Power HCSL (LP-HCSL) outputs to increase edge rates
on long traces, reduce board space, and reduce power
consumption more than 50% from the original 9ZX21501. It is
pin-compatible to the 9ZXL1530 and has the output
terminations integrated. It is suitable for PCI-Express
Gen1/2/3 or QPI/UPI applications, and uses a fixed external
feedback to maintain low drift for demanding QPI/UPI
applications.
Recommended Application
Buffer for Romley, Grantley and Purley Servers
Key Specifications
Cycle-to-cycle jitter: < 50ps
Output-to-output skew: <75ps
Input-to-output delay variation: <50ps
Phase jitter: PCIe Gen3 < 1ps rms
Phase jitter: QPI 9.6GB/s < 0.2ps rms
Block Diagram
Features/Benefits
LP-HCSL outputs; up to 90% IO power reduction, better
signal integrity over long traces
Direct connect to 85transmission lines; eliminates 60
termination resistors, saves 103mm2 area
Pin compatible to the 9ZXL1530; easy upgrade to reduced
board space
64-VFQFPN package; smallest 15 output Z-buffer
Fixed feedback path: ~ 0ps input-to-output delay
9 Selectable SMBus addresses; multiple devices can share
same SMBus segment
Separate VDDIO for outputs; allows maximum power
savings
PLL or bypass mode; PLL can dejitter incoming clock
100MHz & 133.33MHz PLL mode; legacy QPI/UPI support
Selectable PLL BW; minimizes jitter peaking in downstream
PLL's
Spread spectrum compatible; tracks spreading input clock
for EMI reduction
SMBus Interface; unused outputs can be disabled
Output Features
15 - LP-HCSL Differential Output Pairs w/integrated
terminations (Zo = 85)
DIF_IN
DIF_IN#
HIBW_BYPM_LOBW#
100M_133M#
CKPWRGD/PD#
SMB_A0_tri
SMB_A1_tri
SMBDAT
SMBCLK
Logic
Z-PLL
(SS Compatible)
9ZXL1550 REVISION E 11/20/15
1
FBOUT_NC
DIF(14:0)
©2015 Integrated Device Technology, Inc.

                    
                    






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