9ZXL1930 Datasheet: 19-OUTPUT DB1900Z LOW-POWER DERIVATIVE





9ZXL1930 19-OUTPUT DB1900Z LOW-POWER DERIVATIVE Datasheet

Part Number 9ZXL1930
Description 19-OUTPUT DB1900Z LOW-POWER DERIVATIVE
Manufacture IDT
Total Page 18 Pages
PDF Download Download 9ZXL1930 Datasheet PDF

Features: 19-OUTPUT DB1900Z LOW-POWER DERIVATIVE DATASHEET 9ZXL1930 Description The 9ZX L1930 is a low power version of the Int el DB1900Z Differential Buffer utilizin g Low-Power HCSL (LP-HCSL) outputs to r educe power consumption more than 50% f rom the original IDT9ZX21901. It is sui table for PCI-Express Gen1/2/3 or QPI/U PI applications, and uses a fixed exter nal feedback to maintain low drift for demanding QPI/UPI applications. Recomme nded Application Buffer for Romley, Gra ntley and Purley Servers Key Specificat ions • Cycle-to-cycle jitter: < 50ps • Output-to-output skew: <85ps • In put-to-output delay: Fixed at 0 ps • Input-to-output delay variation: <50ps • Phase jitter: PCIe Gen3 < 1ps rms Phase jitter: QPI/UPI 9.6GB/s < 0.2p s rms Features/Benefits • Fixed feed back path; 0ps input-to-output delay 9 Selectable SMBus addresses; Multipl e devices can share same SMBus segment • Separate VDDIO for outputs; allows maximum power savings • PLL or bypass mode; PLL can dejitter .

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19-OUTPUT DB1900Z LOW-POWER DERIVATIVE
DATASHEET
9ZXL1930
Description
The 9ZXL1930 is a low power version of the Intel DB1900Z
Differential Buffer utilizing Low-Power HCSL (LP-HCSL)
outputs to reduce power consumption more than 50% from
the original IDT9ZX21901. It is suitable for PCI-Express
Gen1/2/3 or QPI/UPI applications, and uses a fixed external
feedback to maintain low drift for demanding QPI/UPI
applications.
Recommended Application
Buffer for Romley, Grantley and Purley Servers
Key Specifications
Cycle-to-cycle jitter: < 50ps
Output-to-output skew: <85ps
Input-to-output delay: Fixed at 0 ps
Input-to-output delay variation: <50ps
Phase jitter: PCIe Gen3 < 1ps rms
Phase jitter: QPI/UPI 9.6GB/s < 0.2ps rms
Features/Benefits
Fixed feedback path; 0ps input-to-output delay
9 Selectable SMBus addresses; Multiple devices can
share same SMBus segment
Separate VDDIO for outputs; allows maximum power
savings
PLL or bypass mode; PLL can dejitter incoming clock
Selectable PLL BW; minimizes jitter peaking in
downstream PLL's
Spread spectrum compatible; tracks spreading input
clock for EMI reduction
SMBus Interface; unused outputs can be disabled
100MHz & 133.33MHz PLL mode; Legacy QPI/UPI
support
Differential outputs are Low/Low in power down;
Maximum power savings
Output Features
19 - LP-HCSL Differential Output Pairs
Block Diagram
DIF_IN
DIF_IN#
HIBW_BYPM_LOBW#
100M_133M#
CKPWRGD/PD#
SMB_A0_tri
SMB_A1_tri
SMBDAT
SMBCLK
Logic
Z-PLL
(SS Compatible)
IDT® 19-OUTPUT DB1900Z LOW-POWER DERIVATIVE
1
FBOUT_NC
DIF18
DIF0
9ZXL1930
REV D 112015

                    
                    






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