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ICS874S02I Dataheets PDF



Part Number ICS874S02I
Manufacturers IDT
Logo IDT
Description 1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
Datasheet ICS874S02I DatasheetICS874S02I Datasheet (PDF)

1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR ICS874S02I General Description The ICS874S02I is a highly versatile 1:1 DifferentialICS to-LVDS Clock Generator and a member of the HiPerClockS™ HiPerClockS™ family of High Performance Clock Solutions from IDT. The ICS874S02I has a fully integrated PLL and can be configured as a zero delay buffer, multiplier or divider, and has an output frequency range of 62.5MHz to 1GHz. The reference divider, feedback divider and output divider are each pr.

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1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR ICS874S02I General Description The ICS874S02I is a highly versatile 1:1 DifferentialICS to-LVDS Clock Generator and a member of the HiPerClockS™ HiPerClockS™ family of High Performance Clock Solutions from IDT. The ICS874S02I has a fully integrated PLL and can be configured as a zero delay buffer, multiplier or divider, and has an output frequency range of 62.5MHz to 1GHz. The reference divider, feedback divider and output divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve “zero delay” between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers. Features • One differential LVDS output pair and one differential feedback outpu.


874S02I ICS874S02I 87973I-147


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