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XC9536XL Dataheets PDF



Part Number XC9536XL
Manufacturers Xilinx
Logo Xilinx
Description High Performance CPLD
Datasheet XC9536XL DatasheetXC9536XL Datasheet (PDF)

0 R XC9536XL High Performance CPLD DS058 (v1.9) April 3, 2007 00 Features • 5 ns pin-to-pin logic delays • System frequency up to 178 MHz • 36 macrocells with 800 usable gates • Available in small footprint packages - 44-pin PLCC (34 user I/O pins) - 44-pin VQFP (34 user I/O pins) - 48-pin CSP (36 user I/O pins) - 64-pin VQFP (36 user I/O pins) - Pb-free available for all packages • Optimized for high-performance 3.3V systems - Low power operation - 5V tolerant I/O pins accept 5 V, 3.3V, and .

  XC9536XL   XC9536XL


Document
0 R XC9536XL High Performance CPLD DS058 (v1.9) April 3, 2007 00 Features • 5 ns pin-to-pin logic delays • System frequency up to 178 MHz • 36 macrocells with 800 usable gates • Available in small footprint packages - 44-pin PLCC (34 user I/O pins) - 44-pin VQFP (34 user I/O pins) - 48-pin CSP (36 user I/O pins) - 64-pin VQFP (36 user I/O pins) - Pb-free available for all packages • Optimized for high-performance 3.3V systems - Low power operation - 5V tolerant I/O pins accept 5 V, 3.3V, and 2.5V signals - 3.3V or 2.5V output capability - Advanced 0.35 micron feature size CMOS Fast FLASH™ technology • Advanced system features - In-system programmable - Superior pin-locking and routability with Fast CONNECT™ II switch matrix - Extra wide 54-input Function Blocks - Up to 90 product-terms per macrocell with individual product-term allocation - Local clock inversion with three global and one product-term clocks - Individual output enable per output pin - Input hysteresis.


A2SHB XC9536XL CH452


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