54LS77

4-BIT D LATCH The TTL/MSI SN54 / 74LS75 and SN54 / 74LS77 are latches used as temporary storage for binary information between processing units and input /output or indicator units. Information present at a data (D) input is transferred to the Q output when the Enable is HIGH and the Q output will follow the data input as long as the Enable remains HIGH. When the Enable goes LOW, the information (that was present at the data input at the time the transition occurred) is retained at the Q output until the Enable is permitted to go HIGH. The SN54 / 74LS75 features complementary Q and Q output from a 4-bit latch and is available in the 16-pin packages. For higher component density applications the SN54 / 74LS77 4-bit latch is available in the 14-pin package with Q outputs omitted. CONNECTION DIAGRAMS DIP (TOP VIEW) Q0 Q1 Q1 E0–1 GND Q2 Q2 Q3 16 15 14 13 12 11 10 9 SN54 / 74LS75 1 2 3 4 56 78 Q0 D0 D1 E2–3 VCC D2 D3 Q3 Q0 Q1 E0–1 GND NC Q2 Q3 14 13 12 11 10 9 8 SN54 / 74LS77 123456...