Synchronous SRAM. AS5SP128K36 Datasheet

AS5SP128K36 Datasheet PDF, Equivalent


Part Number

AS5SP128K36

Description

Synchronous SRAM

Manufacture

Micross

Total Page 14 Pages
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AS5SP128K36 Datasheet
Plastic Encapsulated Microcircuit
4.5Mb, 128K x 36, Synchronous SRAM
Pipeline Burst, Single Cycle Deselect
FEATURES
• Synchronous Operation in relation to the input Clock
• 2 Stage Registers resulting in Pipeline operation
• On chip address counter (base +3) for Burst operations
• Self-Timed Write Cycles
• On-Chip Address and Control Registers
• Byte Write support
• Global Write support
• On-Chip low power mode [powerdown] via ZZ pin
• Interleaved or Linear Burst support via Mode pin
• Three Chip Enables for ease of depth expansion without
Data Contention.
• Two Cycle load, Single Cycle Deselect
• Asynchronous Output Enable (OE\)
• Three Pin Burst Control (ADSP\, ADSC\, ADV\)
• 3.3V Core Power Supply
• 3.3V/2.5V IO Power Supply
• JEDEC Standard 100 pin TQFP Package
• Available in Industrial, Enhanced, and Mil-Temperature
Operating Ranges
RoHs compliant options available
DQPc
DQc
DQc
VDDQ
VSSQ
DQc
DQc
DQc
DQc
VSSQ
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSSQ
DQd
DQd
DQd
DQd
VSSQ
VDDQ
DQd
DQd
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SSRAM
AS5SP128K36
SSRAM [SPB]
80 DQPb
79 DQb
78 DQb
77 VDDQ
76 VSSQ
75 DQb
74 DQb
73 DQb
72 DQb
71 VSSQ
70 VDDQ
69 DQb
68 DQb
67 VSS
66 NC
65 VDD
64 ZZ
63 DQa
62 DQa
61 VDDQ
60 VSSQ
59 DQa
58 DQa
57 DQa
56 DQa
55 VSSQ
54 VDDQ
53 DQa
52 DQa
51 DQPa
FAST ACCESS TIMES
Parameter
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol
tCYC
tCD
tOE
200Mhz
5.0
3.0
3.0
166Mhz
6.0
3.5
3.5
BLOCK DIAGRAM
OE\
ZZ
CLK
CE1\
CE2
CE3\
BWE\
BWx\
GW\
ADV
ADSC\
ADSP\
MODE
A0-Ax
CONTROL
BLOCK
BURST CNTL.
Address
Registers
Row
Decode
Column
Decode
I/O Gating and Control
Memory Array
x36
SBP
Synchronous Pipeline
Burst
Two (2) cycle load
One (1) cycle
de-select
One (1) cycle latency
on Mode change
133Mhz
7.5
4.0
4.0
Units
ns
ns
ns
GENERAL DESCRIPTION
The AS5SP128K36 is a 4.5Mb High Performance Synchronous
Pipeline Burst SRAM, available in multiple temperature
screening levels, fabricated using High Performance CMOS
technology and is organized as a 128K x 36. It integrates
address and control registers, a two (2) bit burst address
counter supporting four (4) double-word transfers. Writes are
internally self-timed and synchronous to the rising edge of
clock.
Output Output
Register Driver
Input
Register
The AS5SP128K36 includes advanced control options
including Global Write, Byte Write as well as an Asynchronous
Output enable. Burst Cycle controls are handled by three (3)
input pins, ADV, ADSP\ and ADSC\. Burst operation can be
initiated with either the Address Status Processor (ADSP\) or
DQx, DQPx Address Status Cache controller (ADSC\) inputs. Subsequent
burst addresses are generated internally in the system’s burst
sequence control block and are controlled by Address Advance
(ADV) control input.
AS5SP128K36
Rev. 1.6 10/13
Micross Components reserves the right to change products or specications without notice.
1

AS5SP128K36 Datasheet
SSRAM
AS5SP128K36
PIN DESCRIPTION / ASSIGNMENT TABLE
Signal Name
Clock
Address
Address
Chip Enable
Chip Enable
Global Write Enable
Byte Enables
Byte Write Enable
Output Enable
Address Strobe Controller
Address Strobe from Processor
Address Advance
Power-Down
Data Parity Input/Outputs
Data Input/Outputs
Burst Mode
Power Supply [Core]
Ground [Core]
Power Supply I/O
I/O Ground
No Connection(s)
Symbol
CLK
A0, A1
A
Type
Input
Input
Input(s)
CE1\, CE3\
CE2
GW\
BWa\, BWb\,
BWc\, BWd\
BWE\
OE\
ADSC\
Input
Input
Input
Input
Input
Input
Input
ADSP\
Input
ADV\
ZZ
DQPa, DQPb
DQPc, DQPd
Input
Input
Input/
Output
DQa, DQb, DQc Input/
DQd
Output
MODE
VDD
VSS
VDDQ
VSSQ
NC
Input
Supply
Supply
Supply
Supply
NA
Pin
89
37, 36
35, 34, 33, 32, 100,
99, 82, 81, 44, 45, 46,
47, 48, 49, 50
98, 92
97
88
93, 94, 95, 96
Description
This input registers the address, data, enables, Global and Byte
writes as well as the burst control functions
Low order, Synchronous Address Inputs and Burst counter
address inputs
Synchronous Address Inputs
Active Low True Chip Enables
Active High True Chip Enable
Active Low True Global Write enable. Write to all bits
Active Low True Byte Write enables. Write to byte segments
87
86
85
84
83
64
51, 80, 1, 30
52, 53, 56, 57, 58, 59,
62, 63, 68, 69, 72, 73,
74, 75, 78, 79, 2, 3, 6,
7, 8, 9, 12, 13, 18, 19,
22, 23, 24, 25, 28, 29
31
91, 15, 41, 65
90, 17, 40, 67
4, 11, 20, 27, 54, 61,
70, 77
5, 10, 21, 26, 55, 60,
71, 76
14, 16, 38, 39, 66
38,39,42,43
Active Low True Byte Write Function enable
Active Low True Asynchronous Output enable
Address Strobe from Controller. When asserted LOW, Address is
captured in the address registers and A0-A1 are loaded into the Burst
When ADSP\ and ADSC are both asserted, only ADSP is recognized
Synchronous Address Strobe from Processor. When asserted LOW,
Address is captured in the Address registers, A0-A1 is registered in
the burst counter. When both ADSP\ and ADSC\ or both asserted,
only ADSP\ is recognized. ADSP\ is ignored when CE1\ is HIGH
Advance input Address. When asserted LOW, address in burst
counter is incremented.
Asynchronous, non-time critical Power-down Input control. Places
the chip into an ultra low power mode, with data preserved.
Bidirectional I/O Parity lines. As inputs they reach the memory
array via an input register, the address stored in the register on the
rising edge of clock. As and output, the line delivers the valid data
stored in the array via an output register and output driver. The data
delieverd is from the previous clock period of the READ cycle.
Bidirectional I/O Data lines. As inputs they reach the memory
array via an input register, the address stored in the register on the
rising edge of clock. As and output, the line delivers the valid data
stored in the array via an output register and output driver. The data
delieverd is from the previous clock period of the READ cycle.
Interleaved or Linear Burst mode control
Core Power Supply
Core Power Supply Ground
Isolated Input/Output Buffer Supply
Isolated Input/Output Buffer Ground
No connections to internal silicon
AS5SP128K36
Rev. 1.6 10/13
Micross Components reserves the right to change products or specications without notice.
2


Features Datasheet pdf Plastic Encapsulated Microcircuit 4.5Mb, 128K x 36, Synchronous SRAM Pipeline B urst, Single Cycle Deselect FEATURES Synchronous Operation in relation to the input Clock • 2 Stage Registers r esulting in Pipeline operation • On c hip address counter (base +3) for Burst operations • Self-Timed Write Cycles • On-Chip Address and Control Regist ers • Byte Write support • Global W rite support • On-Chip low power mode [powerdown] via ZZ pin • Interleaved or Linear Burst support via Mode pin Three Chip Enables for ease of depth expansion without Data Contention. • Two Cycle load, Single Cycle Deselect • Asynchronous Output Enable (OE) • Three Pin Burst Control (ADSP, ADSC, A DV) • 3.3V Core Power Supply • 3.3V /2.5V IO Power Supply • JEDEC Standar d 100 pin TQFP Package • Available in Industrial, Enhanced, and Mil-Temperat ure Operating Ranges • RoHs compliant options available DQPc DQc DQc VDDQ V SSQ DQc DQc DQc DQc VSSQ VDDQ DQc DQc NC VDD NC VSS DQd DQd.
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