SN74LS107A FLIP-FLOP Datasheet

SN74LS107A Datasheet, PDF, Equivalent


Part Number

SN74LS107A

Description

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

Manufacture

Motorola

Total Page 4 Pages
Datasheet
Download SN74LS107A Datasheet


SN74LS107A
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54 / 74LS107A is a Dual JK Flip-Flop with individual J, K, Direct
Clear and Clock Pulse inputs. Output changes are initiated by the
HIGH-to-LOW transition of the clock. A LOW signal on CD input overrides the
other inputs and makes the Q output LOW.
The SN54 / 74LS107A is the same as the SN54 / 74LS73A but has corner
power pins.
SN54/74LS107A
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC CD1 CP1
14 13 12
K2
11
CD2 CP2
10 9
J2
8
1234567
J1 Q1 Q1 K1 Q2 Q2 GND
NOTE:
The Flatpak version has the
same pinouts (Connection
Diagram) as the Dual In-Line
Package.
14
1
14
1
J SUFFIX
CERAMIC
CASE 632-08
N SUFFIX
PLASTIC
CASE 646-06
LOGIC SYMBOL
1
2
1J
Q3
8J
Q5
12 CP
9 CP
4K
Q2
CD
11
KQ
CD
6
13
VCC = PIN 14
GND = PIN 7
10
14
1
D SUFFIX
SOIC
CASE 751A-02
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
Supply Voltage
TA Operating Ambient Temperature Range
IOH Output Current — High
IOL Output Current — Low
Min Typ Max Unit
54 4.5 5.0 5.5
74 4.75 5.0 5.25
V
54 – 55 25 125 °C
74 0 25 70
54, 74
– 0.4
mA
54 4.0 mA
74 8.0
FAST AND LS TTL DATA
5-177

SN74LS107A
SN54 / 74LS107A
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Min Typ Max Unit
Test Conditions
VIH Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL Input LOW Voltage
54
74
0.7 Guaranteed Input LOW Voltage for
0.8 V All Inputs
VIK
VOH
Input Clamp Diode Voltage
Output HIGH Voltage
54
74
– 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
2.5 3.5
2.7 3.5
V VCC = MIN, IOH = MAX, VIN = VIH
V or VIL per Truth Table
VOL
Output LOW Voltage
54, 74
74
0.25 0.4
0.35 0.5
V IOL = 4.0 mA
V IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
IIH Input HIGH Current
J, K
Clear
Clock
J, K
Clear
Clock
20
60 µA VCC = MAX, VIN = 2.7 V
80
0.1
0.3 mA VCC = MAX, VIN = 7.0 V
0.4
IIL Input LOW Current
J, K
Clear and Clock
– 0.4
– 0.8
mA
VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1)
– 20 –100 mA VCC = MAX
ICC Power Supply Current
6.0 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Symbol
fMAX
tPLH
tPHL
Parameter
Maximum Clock Frequency
Propagation Delay,
Clock to Output
Limits
Min Typ Max
30 45
15 20
15 20
Unit
MHz
ns
ns
Test Conditions
VCC = 5.0 V
CL = 15 pF
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Symbol
tW
tW
ts
th
Parameter
Clock Pulse Width
Clear Pulse Width
Setup Time
Hold Time
Limits
Min Typ Max
20
25
20
0
Unit
ns
ns
ns
ns
Test Conditions
VCC = 5.0 V
FAST AND LS TTL DATA
5-178


Features DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLO P The SN54 / 74LS107A is a Dual JK Flip -Flop with individual J, K, Direct Clea r and Clock Pulse inputs. Output change s are initiated by the HIGH-to-LOW tran sition of the clock. A LOW signal on CD input overrides the other inputs and m akes the Q output LOW. The SN54 / 74LS1 07A is the same as the SN54 / 74LS73A b ut has corner power pins. SN54/74LS107 A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP- FLOP LOW POWER SCHOTTKY CONNECTION DIA GRAM DIP (TOP VIEW) VCC CD1 CP1 14 13 12 K2 11 CD2 CP2 10 9 J2 8 1234567 J1 Q1 Q1 K1 Q2 Q2 GND NOTE: The Flatpa k version has the same pinouts (Connect ion Diagram) as the Dual In-Line Packag e. 14 1 14 1 J SUFFIX CERAMIC CASE 63 2-08 N SUFFIX PLASTIC CASE 646-06 LOGI C SYMBOL 1 2 1J Q3 8J Q5 12 CP 9 CP 4K Q2 CD 11 KQ CD 6 13 VCC = PIN 14 GND = PIN 7 10 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATIO N SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXD SOIC GUARANTEED OPERATING RANGES Symbol Paramete.
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