SN74LS109A FLIP-FLOP Datasheet

SN74LS109A Datasheet, PDF, Equivalent


Part Number

SN74LS109A

Description

DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP

Manufacture

Motorola

Total Page 4 Pages
Datasheet
Download SN74LS109A Datasheet


SN74LS109A
DUAL JK POSITIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54/ 74LS109A consists of two high speed completely independent
transition clocked JK flip-flops. The clocking operation is independent of rise
and fall times of the clock waveform. The JK design allows operation as a D
flip-flop by simply connecting the J and K pins together.
LOGIC DIAGRAM
SET (SD)
5(11)
CLEAR (CD)
1(15)
CLOCK
4(12)
J
2(14)
K
3(13)
Q
6(10)
Q
7(9)
MODE SELECT — TRUTH TABLE
OPERATING MODE
INPUTS
SD CD J
OUTPUTS
KQQ
Set
Reset (Clear)
*Undetermined
Load “1” (Set)
Hold
Toggle
Load “0” (Reset)
LHXXHL
HLXXLH
L L XXHH
HHh hHL
HH l h q q
HHh l q q
HH l
l LH
* Both outputs will be HIGH while both SD and CD are LOW, but the output states
are unpredictable if SD and CD go HIGH simultaneously.
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output)
l, h (q) = one set-up time prior to the LOW to HIGH clock transition.
SN54/74LS109A
DUAL JK POSITIVE
EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
16
1
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
LOGIC SYMBOL
5 11
2
J SD Q
6 14 J SD Q
4 CP
12
CP
7 13
3 K CD Q
K CD Q
10
9
1 15
VCC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
5-181

SN74LS109A
SN54 / 74LS109A
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
Supply Voltage
TA Operating Ambient Temperature Range
Min Typ Max Unit
54 4.5 5.0 5.5
74 4.75 5.0 5.25
V
54 – 55 25 125 °C
74 0 25 70
IOH Output Current — High
IOL Output Current — Low
54, 74
54
74
– 0.4
4.0
8.0
mA
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Min Typ Max Unit
Test Conditions
VIH Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
VIK
VOH
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
54
74
54
74
0.7
0.8
– 0.65 – 1.5
2.5 3.5
2.7 3.5
VOL
Output LOW Voltage
54, 74
74
0.25 0.4
0.35 0.5
Input HIGH Current
J, K, Clock
IIH Set, Clear
J, K, Clock
Set, Clear
20
40
0.1
0.2
Input LOW Current
IIL J, K, Clock
Set, Clear
– 0.4
– 0.8
IOS Output Short Circuit Current (Note 1) – 20
– 100
ICC Power Supply Current
8.0
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits
Symbol
Parameter
Min Typ Max
fMAX
tPLH
tPHL
Maximum Clock Frequency
Clock, Clear, Set to Output
25 33
13 25
25 40
Guaranteed Input LOW Voltage for
V All Inputs
V VCC = MIN, IIN = – 18 mA
V VCC = MIN, IOH = MAX, VIN = VIH
V or VIL per Truth Table
V IOL = 4.0 mA
V IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
µA VCC = MAX, VIN = 2.7 V
mA VCC = MAX, VIN = 7.0 V
mA VCC = MAX, VIN = 0.4 V
mA VCC = MAX
mA VCC = MAX
Unit
MHz
ns
ns
Test Conditions
VCC = 5.0 V
CL = 15 pF
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Symbol
tW
ts
th
Parameter
Clock High Clear, Set Pulse Width
Data Setup Time — HIGH
Data Setup Time — LOW
Hold time
Min
25
20
20
5.0
Limits
Typ
Max
Unit
ns
ns
ns
ns
Test Conditions
VCC = 5.0 V
FAST AND LS TTL DATA
5-182


Features DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLO P The SN54/ 74LS109A consists of two hi gh speed completely independent transit ion clocked JK flip-flops. The clocking operation is independent of rise and f all times of the clock waveform. The JK design allows operation as a D flip-fl op by simply connecting the J and K pin s together. LOGIC DIAGRAM SET (SD) 5(1 1) CLEAR (CD) 1(15) CLOCK 4(12) J 2(14) K 3(13) Q 6(10) Q 7(9) MODE SELECT TRUTH TABLE OPERATING MODE INPUTS SD CD J OUTPUTS KQQ Set Reset (Clear) *Undetermined Load “1” (Set) Hold Toggle Load “0” (Reset) LHXXHL HL XXLH L L XXHH HHh hHL HH l h q q HH h l q q HH l l LH * Both outputs wil l be HIGH while both SD and CD are LOW, but the output states are unpredictabl e if SD and CD go HIGH simultaneously. H, h = HIGH Voltage Level L, I = LOW Vo ltage Level X = Don’t Care l, h (q) = Lower case letters indicate the state of the referenced input (or output) l, h (q) = one set-up time prior to the LOW to HIGH clock transiti.
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