SN74LS112A FLIP-FLOP Datasheet

SN74LS112A Datasheet, PDF, Equivalent


Part Number

SN74LS112A

Description

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

Manufacture

Motorola

Total Page 4 Pages
Datasheet
Download SN74LS112A Datasheet


SN74LS112A
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and
asynchronous set and clear inputs to each flip-flop. When the clock goes
HIGH, the inputs are enabled and data will be accepted. The logic level of the
J and K inputs may be allowed to change when the clock pulse is HIGH and
the bistable will perform according to the truth table as long as minimum set-up
and hold time are observed. Input data is transferred to the outputs on the
negative-going edge of the clock pulse.
SN54/74LS112A
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
LOGIC DIAGRAM (Each Flip-Flop)
Q
5(9)
CLEAR (CD)
15(14)
J
3(11)
1(13)
CLOCK (CP)
MODE SELECT — TRUTH TABLE
OPERATING MODE
Set
Reset (Clear)
*Undetermined
Toggle
Load “0” (Reset)
Load “1” (Set)
Hold
INPUTS
SD CD
LH
HL
LL
HH
HH
HH
HH
J
X
X
X
h
l
h
l
OUTPUTS
KQQ
XHL
XLH
XHH
hqq
h LH
l HL
l qq
* Both outputs will be HIGH while both SD and CD are LOW, but the output states
are unpredictable if SD and CD go HIGH simultaneously.
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output)
l, h (q) = one set-up time prior to the HIGH to LOW clock transition.
Q
6(7)
SET (SD)
4(10)
K
2(12)
16
1
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
LOGIC SYMBOL
4 10
3
SD
JQ
11 SD
5J
Q
9
1 CP
2 K CD Q
13 CP
12
6
K
Q
CD
7
15 14
VCC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
5-185

SN74LS112A
SN54 / 74LS112A
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
Supply Voltage
TA Operating Ambient Temperature Range
Min Typ Max Unit
54 4.5 5.0 5.5
74 4.75 5.0 5.25
V
54 – 55 25 125 °C
74 0 25 70
IOH Output Current — High
IOL Output Current — Low
54, 74
54
74
– 0.4
4.0
8.0
mA
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Min Typ Max Unit
Test Conditions
VIH Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
VIK
VOH
Input LOW Voltage
54
74
0.7
0.8
Input Clamp Diode Voltage
– 0.65 – 1.5
Output HIGH Voltage
54 2.5 3.5
74 2.7 3.5
VOL
Output LOW Voltage
54, 74
74
0.25 0.4
0.35 0.5
J, K
Set, Clear
Clock
IIH
Input HIGH Current
J, K
Set, Clear
Clock
20
60
80
0.1
0.3
0.4
IIL
Input LOW Current J, K
Clear, Set, Clk
– 0.4
– 0.8
IOS
Short Circuit Current (Note 1)
– 20
– 100
ICC Power Supply Current
6.0
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits
Symbol
Parameter
Min Typ Max
fMAX
tPLH
tPHL
Maximum Clock Frequency
Propagation Delay, Clock
Clear, Set to Output
30 45
15 20
15 20
V
V
V
V
V
V
µA
mA
mA
mA
mA
Unit
MHz
ns
ns
Guaranteed Input LOW Voltage for
All Inputs
VCC = MIN, IIN = – 18 mA
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
IOL = 4.0 mA
IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VCC = MAX, VIN = 2.7 V
VCC = MAX, VIN = 7.0 V
VCC = MAX, VIN = 0.4 V
VCC = MAX
VCC = MAX
Test Conditions
VCC = 5.0 V
CL = 15 pF
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Symbol
tW
tW
ts
th
Parameter
Clock Pulse Width High
Clear, Set Pulse Width
Setup Time
Hold Time
Min
20
25
20
0
Limits
Typ
Max
Unit
ns
ns
ns
ns
Test Conditions
VCC = 5.0 V
FAST AND LS TTL DATA
5-186


Features DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLO P The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and a synchronous set and clear inputs to eac h flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistab le will perform according to the truth table as long as minimum set-up and hol d time are observed. Input data is tran sferred to the outputs on the negative- going edge of the clock pulse. SN54/74 LS112A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY LOGIC DIA GRAM (Each Flip-Flop) Q 5(9) CLEAR (CD ) 15(14) J 3(11) 1(13) CLOCK (CP) MOD E SELECT — TRUTH TABLE OPERATING MOD E Set Reset (Clear) *Undetermined Toggl e Load “0” (Reset) Load “1” (Se t) Hold INPUTS SD CD LH HL LL HH HH H H HH J X X X h l h l OUTPUTS KQQ XHL XLH XHH hqq h LH l HL l qq * Both outp uts will be HIGH while both SD and CD are LOW, but the output s.
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