SN74LS113A FLIP-FLOP Datasheet

SN74LS113A Datasheet, PDF, Equivalent


Part Number

SN74LS113A

Description

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

Manufacture

Motorola

Total Page 4 Pages
Datasheet
Download SN74LS113A Datasheet


SN74LS113A
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54 / 74LS113A offers individual J, K, set, and clock inputs. These
monolithic dual flip-flops are designed so that when the clock goes HIGH, the
inputs are enabled and data will be accepted. The logic level of the J and K
inputs may be allowed to change when the clock pulse is HIGH and the
bistable will perform according to the truth table as long as minimum setup
times are observed. Input data is transferred to the outputs on the
negative-going edge of the clock pulse.
SN54/74LS113A
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
LOGIC DIAGRAM (Each Flip-Flop)
Q
5(9)
J
3(11)
1(13)
CLOCK (CP)
Q
6(8)
SET (SD)
4(10)
K
2(12)
MODE SELECT — TRUTH TABLE
OPERATING MODE
INPUTS
SD J
K
OUTPUTS
QQ
Set
Toggle
Load “0” (Reset)
Load “1” (Set)
Hold
L XXH L
Hh h q q
H l hLH
Hh l HL
Hl l qq
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output)
l, h (q) = one set-up time prior to the HIGH to LOW clock transition.
14
1
J SUFFIX
CERAMIC
CASE 632-08
14
1
N SUFFIX
PLASTIC
CASE 646-06
14
1
D SUFFIX
SOIC
CASE 751A-02
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
LOGIC SYMBOL
4 10
3
SD
JQ
11 SD
5J
Q
9
1 CP
2K
Q
13 CP
12
6K
Q
8
VCC = PIN 14
GND = PIN 7
FAST AND LS TTL DATA
5-189

SN74LS113A
SN54 / 74LS113A
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
Supply Voltage
TA Operating Ambient Temperature Range
IOH Output Current — High
IOL Output Current — Low
Min Typ Max Unit
54 4.5 5.0 5.5
74 4.75 5.0 5.25
V
54 – 55 25 125 °C
74 0 25 70
54, 74
– 0.4
mA
54 4.0 mA
74 8.0
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Symbol
Parameter
Limits
Min Typ Max
Unit
Test Conditions
VIH Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
54
VIL
Input LOW Voltage
74
0.7 Guaranteed Input LOW Voltage for
0.8 V All Inputs
VIK
VOH
Input Clamp Diode Voltage
Output HIGH Voltage
54
74
– 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
2.5 3.5
2.7 3.5
V VCC = MIN, IOH = MAX, VIN = VIH
V or VIL per Truth Table
VOL
Output LOW Voltage
54, 74
74
0.25 0.4
0.35 0.5
V IOL = 4.0 mA
V IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
J, K
Set
Clock
IIH
Input HIGH Current
J, K
Set
Clock
20
60 µA VCC = MAX, VIN = 2.7 V
80
0.1
0.3 mA VCC = MAX, VIN = 7.0 V
0.4
IIL
Input LOW Current
J, K
Set, Clock
– 0.4
– 0.8
mA
VCC = MAX, VIN = 0.4 V
IOS
Short Circuit Current (Note 1)
– 20
– 100 mA VCC = MAX
ICC Power Supply Current
6.0
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
mA VCC = MAX
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits
Symbol
Parameter
Min Typ Max
fMAX
tPLH
tPHL
Maximum Clock Frequency
Propagation Delay, Clock
Set to Output
30 45
15 20
15 20
Unit
MHz
ns
ns
Test Conditions
VCC = 5.0 V
CL = 15 pF
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Symbol
tW
tW
ts
th
Parameter
Clock Pulse Width High
Set Pulse Width
Setup Time
Hold Time
Min
20
25
20
0
Limits
Typ
Max
Unit
ns
ns
ns
ns
Test Conditions
VCC = 5.0 V
FAST AND LS TTL DATA
5-190


Features DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLO P The SN54 / 74LS113A offers individual J, K, set, and clock inputs. These mon olithic dual flip-flops are designed so that when the clock goes HIGH, the inp uts are enabled and data will be accept ed. The logic level of the J and K inpu ts may be allowed to change when the cl ock pulse is HIGH and the bistable will perform according to the truth table a s long as minimum setup times are obser ved. Input data is transferred to the o utputs on the negative-going edge of th e clock pulse. SN54/74LS113A DUAL JK N EGATIVE EDGE-TRIGGERED FLIP-FLOP LOW PO WER SCHOTTKY LOGIC DIAGRAM (Each Flip- Flop) Q 5(9) J 3(11) 1(13) CLOCK (CP) Q 6(8) SET (SD) 4(10) K 2(12) MODE S ELECT — TRUTH TABLE OPERATING MODE INPUTS SD J K OUTPUTS QQ Set Toggle Load “0” (Reset) Load “1” (Set ) Hold L XXH L Hh h q q H l hLH Hh l H L Hl l qq H, h = HIGH Voltage Level L, I = LOW Voltage Level X = Don’t Care l, h (q) = Lower case letters indicate the state of the refere.
Keywords SN74LS113A, datasheet, pdf, Motorola, DUAL, JK, NEGATIVE, EDGE-TRIGGERED, FLIP-FLOP, N74LS113A, 74LS113A, 4LS113A, SN74LS113, SN74LS11, SN74LS1, Equivalent, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute




@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)