SN74LS169 COUNTERS Datasheet

SN74LS169 Datasheet, PDF, Equivalent


Part Number

SN74LS169

Description

BCD DECADE/MODULO 16 BINARY SYNCHRONOUS BI-DIRECTIONAL COUNTERS

Manufacture

Motorola

Total Page 8 Pages
Datasheet
Download SN74LS169 Datasheet


SN74LS169
BCD DECADE/MODULO
16 BINARY SYNCHRONOUS
BI-DIRECTIONAL COUNTERS
The SN54 / 74LS168 and SN54 / 74LS169 are fully synchronous 4-stage
up/down counters featuring a preset capability for programmable operation,
carry lookahead for easy cascading and a U/ D input to control the direction
of counting. The SN54 / 74LS168 counts in a BCD decade (8, 4, 2, 1)
sequence, while the SN54 / 74LS169 operates in a Modulo 16 binary
sequence. All state changes, whether in counting or parallel loading, are
initiated by the LOW-to-HIGH transition of the clock.
Low Power Dissipation 100 mW Typical
High-Speed Count Frequency 30 MHz Typical
Fully Synchronous Operation
Full Carry Lookahead for Easy Cascading
Single Up / Down Control Input
Positive Edge-Trigger Operation
Input Clamp Diodes Limit High-Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC
16
TC
15
Q0
14
Q1
13
Q2
12
Q3
11
CET
10
PE
9
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
1
U/D
2
CP
3
P0
4
P1
5
P2
6
P3
78
CEP GND
PIN NAMES
LOADING (Note a)
HIGH
LOW
CEP Count Enable Parallel (Active LOW) Input
0.5 U.L. 0.25 U.L.
CET Count Enable Trickle (Active LOW) Input
1.0 U.L.
0.5 U.L.
CP Clock Pulse (Active positive going edge) Input 0.5 U.L. 0.25 U.L.
PE Parallel Enable (Active LOW) Input
0.5 U.L. 0.25 U.L.
U/D Up-Down Count Control Input
0.5 U.L. 0.25 U.L.
P0–P3 Parallel Data Inputs
Q0–Q3 Flip-Flop Outputs
TC Terminal Count (Active LOW) Output
0.5 U.L.
10 U.L.
10 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
SN54/74LS168
SN54/74LS169
BCD DECADE/ MODULO
16 BINARY SYNCHRONOUS
BI-DIRECTIONAL COUNTERS
LOW POWER SCHOTTKY
16
1
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
93
4
56
1
7
10
2
PE
U/D
P0
P1
CEP
CET
P2 P3
TC
CP
Q0 Q1 Q2 Q3
15
14 13 12 11
VCC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
5-302

SN74LS169
SN54/74LS168 SN54/74LS169
SN54/ 74LS168
UP / DOWN DECADE COUNTER
STATE DIAGRAMS
01234
0
SN54 / 74LS169
123
4
15
5
15
5
Count Up
14
6
Count Down
14
6
13
7
13
7
12 11 10
9
8
SN54 / 74LS168
UP: TC = Q0 Q3 (U / D)
DOWN: TC = Q0 Q1 Q2 Q3 (U / D)
12 11 10
9
8
SN54 / 74LS169
UP: TC = Q0 Q1 Q2 Q3 (U / D)
DOWN: TC = Q0 Q1 Q2 Q3 (U / D)
PE
CEP
CET
U/D
P0
LOGIC DIAGRAMS
SN54 / 74LS168
P1
P2
P3
TC
CP
CP
D
Q0
Q1
Q2
FAST AND LS TTL DATA
5-303
Q3


Features BCD DECADE/MODULO 16 BINARY SYNCHRONOUS BI-DIRECTIONAL COUNTERS The SN54 / 74LS 168 and SN54 / 74LS169 are fully synchr onous 4-stage up/down counters featurin g a preset capability for programmable operation, carry lookahead for easy cas cading and a U/ D input to control the direction of counting. The SN54 / 74LS1 68 counts in a BCD decade (8, 4, 2, 1) sequence, while the SN54 / 74LS169 oper ates in a Modulo 16 binary sequence. Al l state changes, whether in counting or parallel loading, are initiated by the LOW-to-HIGH transition of the clock. Low Power Dissipation 100 mW Typical • High-Speed Count Frequency 30 MHz Typical • Fully Synchronous Operation • Full Carry Lookahead for Easy Casc ading • Single Up / Down Control Inpu t • Positive Edge-Trigger Operation Input Clamp Diodes Limit High-Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 TC 15 Q0 14 Q1 13 Q2 12 Q3 11 CET 10 PE 9 NOTE : The Flatpak version has the same pinouts (Connection Diagram).
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