MOSFET. FDMD84100 Datasheet

FDMD84100 Datasheet PDF, Equivalent


Part Number

FDMD84100

Description

MOSFET

Manufacture

Fairchild Semiconductor

Total Page 7 Pages
PDF Download
Download FDMD84100 Datasheet PDF


FDMD84100 Datasheet
June 2016
FDMD84100
Dual N-Channel PowerTrench® MOSFET
100 V, 21 A, 20 mΩ
Features
General Description
„ Max rDS(on) = 20 mΩ at VGS = 10 V, ID = 7 A
„ Max rDS(on) = 32 mΩ at VGS = 6 V, ID = 5.5 A
„ Ideal for flexible layout in secondary side synchronous
rectification
This package integrates two N-Channel devices connected
internally in common-source configuration. This enables very
low package parasitics and optimized thermal path to the
common source pad on the bottom. Provides a very small
footprint (3.3 x 5 mm) for higher power density.
„ Termination is Lead-free and RoHS Compliant
„ 100% UIL tested
Applications
„ Isolated DC-DC Synchronous Rectifiers
„ Common Ground Load Switches
Top
Pin 1
D2
D2
D2
G2
Bottom
S1/S2
Power 3.3 x 5
Pin 1
G1
D1
D1
D1
G1 1
D1 2
D1 3
D1 4
S1,S2 to backside
8 D2
7 D2
6 D2
5 G2
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
ID
EAS
PD
TJ, TSTG
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current
-Continuous
-Continuous
-Pulsed
TC = 25 °C
TA = 25 °C
Single Pulse Avalanche Energy
Power Dissipation
TC = 25 °C
Power Dissipation
TA = 25 °C
Operating and Storage Junction Temperature Range
Thermal Characteristics
(Note 1a)
(Note 4)
(Note 3)
(Note 1a)
Ratings
100
±20
21
7
80
121
23
2.1
-55 to +150
Units
V
V
A
mJ
W
°C
RθJC
RθJA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
Package Marking and Ordering Information
(Note 1a)
5.3
60
°C/W
Device Marking
84100
Device
FDMD84100
Package
Power 3.3 x 5
Reel Size
13 ’’
Tape Width
12 mm
Quantity
3000 units
©2014 Fairchild Semiconductor Corporation
FDMD84100 Rev.1.1
1
www.fairchildsemi.com

FDMD84100 Datasheet
Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min Typ Max Units
Off Characteristics
BVDSS
ΔBVDSS
ΔTJ
IDSS
IGSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
ID = 250 μA, VGS = 0 V
100
V
ID = 250 μA, referenced to 25 °C
74 mV/°C
VDS = 80 V, VGS = 0 V
VGS = ±20 V, VDS = 0 V
1
±100
μA
nA
On Characteristics
VGS(th)
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
rDS(on)
Static Drain to Source On Resistance
gFS Forward Transconductance
VGS = VDS, ID = 250 μA
ID = 250 μA, referenced to 25 °C
VGS = 10 V, ID = 7 A
VGS = 6 V, ID = 5.5 A
VGS = 10 V, ID = 7 A, TJ = 125 °C
VDD = 5 V, ID = 7 A
2
3.1 4 V
-9 mV/°C
16 20
24 32 mΩ
30 38
17 S
Dynamic Characteristics
Ciss
Coss
Crss
Rg
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
VDS = 50 V, VGS = 0 V
f = 1 MHz
734 980 pF
168 225 pF
6.6 15 pF
0.1 1.3 3 Ω
Switching Characteristics
td(on)
tr
td(off)
tf
Qg(TOT)
Qgs
Qgd
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
VDD = 50 V, ID = 7 A
VGS = 10 V, RGEN = 6 Ω
VGS = 0 V to 10 V
VGS = 0 V to 6 V VDD = 50 V
ID = 7 A
8.4 17 ns
2.6 10 ns
14 25 ns
2.8 10 ns
11 16 nC
7.3 11 nC
3.4 nC
2.5 nC
Drain-Source Diode Characteristics
VSD
Source to Drain Diode Forward Voltage
VGS = 0 V, IS = 7 A
(Note 2)
trr Reverse Recovery Time
Qrr Reverse Recovery Charge
IF = 7 A, di/dt = 100 A/μs
0.8 1.2
V
43 70 ns
44 71 nC
NOTES:
1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by
the user's board design.
a. 60 °C/W when mounted on
a 1 in2 pad of 2 oz copper
b.160 °C/W when mounted on
a minimum pad of 2 oz copper
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0 %.
3. EAS of 121 mJ is based on starting TJ = 25 oC, L = 3 mH, IAS = 9 A, VDD = 100 V, VGS = 10 V. 100% tested at L = 0.1 mH, IAS = 30 A.
4. Pulse Id refers to Figure.11 Forward Bias Safe Operation Area.
©2014 Fairchild Semiconductor Corporation
FDMD84100 Rev.1.1
2
www.fairchildsemi.com


Features Datasheet pdf FDMD84100 Dual N-Channel PowerTrench® M OSFET June 2016 FDMD84100 Dual N-Chan nel PowerTrench® MOSFET 100 V, 21 A, 2 0 mΩ Features General Description Max rDS(on) = 20 mΩ at VGS = 10 V, I D = 7 A „ Max rDS(on) = 32 mΩ at VGS = 6 V, ID = 5.5 A „ Ideal for flexible layout in secondary side synchronous r ectification This package integrates t wo N-Channel devices connected internal ly in common-source configuration. This enables very low package parasitics an d optimized thermal path to the common source pad on the bottom. Provides a ve ry small footprint (3.3 x 5 mm) for hig her power density. „ Termination is L ead-free and RoHS Compliant „ 100% UIL tested Applications „ Isolated DC-DC Synchronous Rectifiers „ Common Grou nd Load Switches Top Pin 1 D2 D2 D2 G 2 Bottom S1/S2 Power 3.3 x 5 Pin 1 G 1 D1 D1 D1 G1 1 D1 2 D1 3 D1 4 S1,S2 to backside 8 D2 7 D2 6 D2 5 G2 MOSFE T Maximum Ratings TA = 25 °C unless ot herwise noted Symbol VDS VGS ID EAS PD TJ, TSTG Parameter Dr.
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