MOSFET. FDG8850NZ Datasheet

FDG8850NZ Datasheet PDF, Equivalent


Part Number

FDG8850NZ

Description

MOSFET

Manufacture

Fairchild Semiconductor

Total Page 6 Pages
PDF Download
Download FDG8850NZ Datasheet PDF


FDG8850NZ Datasheet
April 2007
FDG8850NZ
Dual N-Channel PowerTrench® MOSFET
tm
30V,0.75A,0.4Ω
Features
„ Max rDS(on) = 0.4Ω at VGS = 4.5V, ID = 0.75A
„ Max rDS(on) = 0.5Ω at VGS = 2.7V, ID = 0.67A
„ Very low level gate drive requirements allowing operation
in 3V circuits(VGS(th) <1.5V)
„ Very small package outline SC70-6
„ RoHS Compliant
General Description
This dual N-Channel logic level enhancement mode field effect
transistors are produced using Fairchild’s proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance. This device
has been designed especially for low voltage applications as
a replacement for bipolar digital transistors and small signal
MOSFETs. Since bias resistors are not required, this dual digital
FET can replace several different digital transistors, with differ-
ent bias resistor values.
G2
D1
S2
SC70-6
Pin 1
D2
G1
S1
Q1
S1
G1
Q2
D2
D1
G2
S2
MOSFET Maximum Ratings TA = 25°C unless otherwise noted
Symbol
VDS
VGS
ID
PD
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current
-Continuous
-Pulsed
Power Dissipation for Single Operation
TJ, TSTG
Operating and Storage Junction Temperature Range
Thermal Characteristics
RθJA
RθJA
Thermal Resistance, Junction to Ambient Single operation
Thermal Resistance, Junction to Ambient Single operation
Package Marking and Ordering Information
Device Marking
.50
Device
FDG8850NZ
Reel Size
7”
(Note 1a)
(Note 1b)
Ratings
30
±12
0.75
2.2
0.36
0.30
–55 to +150
Units
V
V
A
W
°C
(Note 1a)
(Note 1b)
350
415
°C/W
Tape Width
8mm
Quantity
3000 units
©2007 Fairchild Semiconductor Corporation
FDG8850NZ Rev.B
1
www.fairchildsemi.com

FDG8850NZ Datasheet
Electrical Characteristics TJ = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min Typ Max Units
Off Characteristics
BVDSS
ΔBVDSS
ΔTJ
IDSS
IGSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
ID = 250μA, VGS = 0V
ID = 250μA, referenced to 25°C
VDS = 24V, VGS = 0V
VGS = ±12V, VDS= 0V
30
25
V
mV/°C
1 μA
±10 μA
On Characteristics
VGS(th)
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
rDS(on)
Static Drain to Source On Resistance
gFS Forward Transconductance
VGS = VDS, ID = 250μA
0.65 1.0
1.5
V
ID = 250μA, referenced to 25°C
–3.0 mV/°C
VGS = 4.5V, ID = 0.75A
VGS = 2.7V, ID = 0.67A
VGS = 4.5V, ID = 0.75A ,TJ = 125°C
VDS = 5V, ID = 0.75A
0.25 0.4
0.29 0.5
0.36 0.6
3
Ω
S
Dynamic Characteristics
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
VDS = 10V, VGS = 0V, f= 1MHZ
90 120
20 30
15 25
pF
pF
pF
Switching Characteristics (note 2)
td(on)
tr
td(off)
tf
Qg
Qgs
Qgd
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
VDD = 5V, ID = 0.5A,
VGS = 4.5V,RGEN = 6Ω
VGS =4.5V, VDD = 5V, ID = 0.75A
4
1
9
1
1.03
0.29
0.17
10
10
18
10
1.44
ns
ns
ns
ns
nC
nC
nC
Drain-Source Diode Characteristics and Maximum Ratings
IS Maximum Continuous Drain-Source Diode Forward Current
VSD
Source to Drain Diode Forward Voltage VGS = 0V, IS = 0.3A
(Note 2)
0.3
0.76 1.2
A
V
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.
RθJC is guaranteed by design while RθJA is determined by the user's board design.
a. 350°C/W when mounted on a
1 in2 pad of 2 oz copper .
b. 415°C/W when mounted on a minimum pad
of 2 oz copper.
Scale 1:1 on letter size paper.
2. Pulse Test: Pulse Width < 300μs, Duty cycle < 2.0%.
©2007 Fairchild Semiconductor Corporation
FDG8850NZ Rev.B
2
www.fairchildsemi.com


Features Datasheet pdf FDG8850NZ Dual N-Channel PowerTrench® M OSFET April 2007 FDG8850NZ Dual N-Cha nnel PowerTrench® MOSFET tm 30V,0.75 A,0.4Ω Features „ Max rDS(on) = 0.4 at VGS = 4.5V, ID = 0.75A „ Max rDS( on) = 0.5Ω at VGS = 2.7V, ID = 0.67A Very low level gate drive requirement s allowing operation in 3V circuits(VGS (th) <1.5V) „ Very small package outli ne SC70-6 „ RoHS Compliant General De scription This dual N-Channel logic lev el enhancement mode field effect transi stors are produced using Fairchild’s proprietary, high cell density, DMOS te chnology. This very high density proces s is especially tailored to minimize on -state resistance. This device has been designed especially for low voltage ap plications as a replacement for bipolar digital transistors and small signal M OSFETs. Since bias resistors are not re quired, this dual digital FET can repla ce several different digital transistor s, with different bias resistor values. G2 D1 S2 SC70-6 Pin 1 D2 G1 S1 Q1 S1 G1 Q2 D2 D1 G2 S2 .
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