MOSFET. FDMS3606AS Datasheet

FDMS3606AS Datasheet PDF, Equivalent


Part Number

FDMS3606AS

Description

MOSFET

Manufacture

Fairchild Semiconductor

Total Page 16 Pages
PDF Download
Download FDMS3606AS Datasheet PDF


FDMS3606AS Datasheet
FDMS3606AS
PowerTrench® Power Stage
September 2011
30 V Asymmetric Dual N-Channel MOSFET
Features
General Description
Q1: N-Channel
„ Max rDS(on) = 8 mΩ at VGS = 10 V, ID = 13 A
„ Max rDS(on) = 11 mΩ at VGS = 4.5 V, ID = 11 A
Q2: N-Channel
„ Max rDS(on) = 1.9 mΩ at VGS = 10 V, ID = 27 A
„ Max rDS(on) = 2.8 mΩ at VGS = 4.5 V, ID = 23 A
„ Low inductance packaging shortens rise/fall times, resulting in
lower switching losses
„ MOSFET integration enables optimum layout for lower circuit
inductance and reduced switch node ringing
„ RoHS Compliant
This device includes two specialized N-Channel MOSFETs in a
dual PQFN package. The switch node has been internally
connected to enable easy placement and routing of synchronous
buck converters. The control MOSFET (Q1) and synchronous
SyncFET (Q2) have been designed to provide optimal power
efficiency.
Applications
„ Computing
„ Communications
„ General Purpose Point of Load
„ Notebook VCORE
„ Sever
G1 D1 D1 D1
D1
PHASE
(S1/D2)
G2S2S2 S2
Top
Power 56
Bottom
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
ID
EAS
PD
TJ, TSTG
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous (Package limited)
-Continuous (Silicon limited)
-Continuous
-Pulsed
Single Pulse Avalanche Energy
Power Dissipation for Single Operation
Power Dissipation for Single Operation
Operating and Storage Junction Temperature Range
Thermal Characteristics
RθJA
RθJA
RθJC
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Case
Package Marking and Ordering Information
S2 5
S2 6
S2 7
G2 8
Q2 4 D1
PHASE
3 D1
2 D1
Q1 1 G1
(Note 3)
TC = 25 °C
TC = 25 °C
TA = 25 °C
TA = 25 °C
TA = 25 °C
Q1 Q2
30 30
±20 ±20
30 40
60
131a
148
271b
40
404
2.21a
1.01c
100
1625
2.51b
1.01d
-55 to +150
Units
V
V
A
mJ
W
°C
571a
1251c
3.5
501b
1201d
2
°C/W
Device Marking
Device
22CA
N9CC
FDMS3606AS
©2011 Fairchild Semiconductor Corporation
FDMS3606AS Rev.C4
Package
Power 56
1
Reel Size
13 ”
Tape Width
12 mm
Quantity
3000 units
www.fairchildsemi.com

FDMS3606AS Datasheet
Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Off Characteristics
BVDSS
ΔBVDSS
ΔTJ
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
ID = 250 μA, VGS = 0 V
ID = 1 mA, VGS = 0 V
ID = 250 μA, referenced to 25 °C
ID = 10 mA, referenced to 25 °C
IDSS
Zero Gate Voltage Drain Current
VDS = 24 V, VGS = 0 V
IGSS
Gate to Source Leakage Current,
Forward
VGS = 20 V, VDS= 0 V
Type Min
Q1 30
Q2 30
Q1
Q2
Q1
Q2
Q1
Q2
Typ
15
20
Max Units
V
mV/°C
1 μA
500 μA
100 nA
100 nA
On Characteristics
VGS(th)
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
rDS(on)
Drain to Source On Resistance
gFS Forward Transconductance
Dynamic Characteristics
Ciss Input Capacitance
Coss
Output Capacitance
Crss Reverse Transfer Capacitance
Rg Gate Resistance
VGS = VDS, ID = 250 μA
VGS = VDS, ID = 1 mA
Q1 1.1
2
Q2 1.1 1.8
2.7
3
V
ID = 250 μA, referenced to 25 °C
ID = 10 mA, referenced to 25 °C
Q1
Q2
-6
-5
mV/°C
VGS = 10 V, ID = 13 A
VGS = 4.5 V, ID = 11 A
VGS = 10 V, ID = 13 A , TJ = 125 °C
VGS = 10 V, ID = 27 A
VGS = 4.5 V, ID = 23 A
VGS = 10 V, ID = 27 A , TJ = 125 °C
Q1
Q2
5.8 8
8.5 11
7.8 10.8
mΩ
1.4 1.9
2 2.8
1.9 2.8
VDS = 5 V, ID = 13 A
VDS = 5 V, ID = 27 A
Q1 61
Q2 154
S
Q1:
VDS = 15 V, VGS = 0 V, f = 1 MHZ
Q2:
VDS = 15 V, VGS = 0 V, f = 1 MHZ
Q1
Q2
Q1
Q2
Q1
Q2
1273
4129
461
1527
50
98
1695
5490
615
2030
75
150
pF
pF
pF
Q1 0.2 0.6
Q2 0.2 0.8
2
3
Ω
Switching Characteristics
td(on)
Turn-On Delay Time
tr Rise Time
td(off)
Turn-Off Delay Time
tf Fall Time
Qg Total Gate Charge
Qg Total Gate Charge
Qgs Gate to Source Gate Charge
Qgd Gate to Drain “Miller” Charge
Q1:
VDD = 15 V, ID = 13 A, RGEN = 6 Ω
Q2:
VDD = 15 V, ID = 27 A, RGEN = 6 Ω
VGS = 0 V to 10 V Q1
VDD = 15 V,
VGS = 0 V to 4.5 V ID = 13 A
Q2
VDD = 15 V,
ID = 27 A
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
8.2
15
16
27
ns
2.5
5.5
10
11
ns
20
36
32
58
ns
2.2
3.4
10
10
ns
21
59
29
83
nC
10
27
14
38
nC
3.9
12
nC
3.1
5.7
nC
©2011 Fairchild Semiconductor Corporation
FDMS3606AS Rev.C4
2
www.fairchildsemi.com


Features Datasheet pdf FDMS3606AS PowerTrench® Power Stage FD MS3606AS PowerTrench® Power Stage Sep tember 2011 30 V Asymmetric Dual N-Cha nnel MOSFET Features General Descript ion Q1: N-Channel „ Max rDS(on) = 8 m Ω at VGS = 10 V, ID = 13 A „ Max rDS( on) = 11 mΩ at VGS = 4.5 V, ID = 11 A Q2: N-Channel „ Max rDS(on) = 1.9 mΩ at VGS = 10 V, ID = 27 A „ Max rDS(on) = 2.8 mΩ at VGS = 4.5 V, ID = 23 A „ Low inductance packaging shortens rise /fall times, resulting in lower switchi ng losses „ MOSFET integration enables optimum layout for lower circuit induc tance and reduced switch node ringing RoHS Compliant This device includes two specialized N-Channel MOSFETs in a dual PQFN package. The switch node has been internally connected to enable eas y placement and routing of synchronous buck converters. The control MOSFET (Q1 ) and synchronous SyncFET (Q2) have bee n designed to provide optimal power eff iciency. Applications „ Computing „ C ommunications „ General Purpose Point of Load „ Notebook VCOR.
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