813N252I-09 Datasheet PDF | IDT





(PDF) 813N252I-09 Datasheet PDF

Part Number 813N252I-09
Description VCXO Jitter Attenuator & FemtoClock Multiplier
Manufacture IDT
Total Page 23 Pages
PDF Download Download 813N252I-09 Datasheet PDF

Features: VCXO Jitter Attenuator & FemtoClock® Mu ltiplier 813N252I-09 Datasheet Genera l Description The 813N252I-09 is a PLL based synchronous multiplier that is op timized for PDH or SONET to Ethernet cl ock jitter attenuation and frequency tr anslation. The device contains two inte rnal frequency multiplication stages th at are cascaded in series. The first st age is a VCXO PLL that is optimized to provide reference clock jitter attenuat ion. The second stage is a FemtoClock frequency multiplier that provides the low jitter, high frequency Ethernet ou tput clock that easily meets Gigabit an d 10 Gigabit Ethernet jitter requiremen ts. Pre-divider and output divider mult iplication ratios are selected using de vice selection control pins. The multip lication ratios are optimized to suppor t most common clock rates used in PDH, SONET and Ethernet applications. The VC XO requires the use of an external, ine xpensive pullable crystal. The VCXO use s external passive loop filter components which allows configur.

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813N252I-09 datasheet
VCXO Jitter Attenuator &
FemtoClock® Multiplier
813N252I-09
Datasheet
General Description
The 813N252I-09 is a PLL based synchronous multiplier that is
optimized for PDH or SONET to Ethernet clock jitter attenuation and
frequency translation. The device contains two internal frequency
multiplication stages that are cascaded in series. The first stage is a
VCXO PLL that is optimized to provide reference clock jitter
attenuation. The second stage is a FemtoClock™frequency multiplier
that provides the low jitter, high frequency Ethernet output clock that
easily meets Gigabit and 10 Gigabit Ethernet jitter requirements.
Pre-divider and output divider multiplication ratios are selected using
device selection control pins. The multiplication ratios are optimized
to support most common clock rates used in PDH, SONET and
Ethernet applications. The VCXO requires the use of an external,
inexpensive pullable crystal. The VCXO uses external passive loop
filter components which allows configuration of the PLL loop
bandwidth and damping characteristics. The device is packaged in a
space-saving 32-VFQFN package and supports industrial
temperature range.
Features
Two LVPECL output pairs
Each output supports independent frequency selection at 25MHz,
125MHz, 156.25MHz and 312.5MHz
Two differential inputs support the following input types: LVPECL,
LVDS, LVHSTL, SSTL, HCSL
Accepts input frequencies from 8kHz to 155.52MHz including
8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz,
125MHz and 155.52MHz
Attenuates the phase jitter of the input clock by using a low-cost
pullable fundamental mode VCXO crystal
VCXO PLL bandwidth can be optimized for jitter attenuation and
reference tracking using external loop filter connection
FemtoClock frequency multiplier provides low jitter, high frequency
output
Absolute pull range: 50ppm
FemtoClock VCO frequency: 625MHz
RMS phase jitter @ 125MHz, using a 25MHz crystal
(12kHz – 20MHz): 0.25ps (typical) and 0.35ps (maximum)
3.3V supply voltage
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Pin Assignment
32 31 30 29 28 27 26 25
LF1 1
24 VEE
LF0 2
23 nQB
ISET 3
22 QB
VEE 4
21 VCCO
CLK_SEL 5
20 nQA
VCC 6
19 QA
RESERVED 7
18 VEE
VEE 8
17 ODASEL_0
9 10 11 12 13 14 15 16
813N252I-09
32 Lead VFQFN
5mm x 5mm x 0.925mm package body
3.15mm x 3.15mm EPad
K Package
Top View
©2015 Integrated Device Technology, Inc.
1
Revision C, December 10, 2015

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