NG Multiplier. 813N252DI-02 Datasheet

813N252DI-02 Datasheet PDF, Equivalent


Part Number

813N252DI-02

Description

Jitter Attenuator & FemtoClock NG Multiplier

Manufacture

IDT

Total Page 23 Pages
PDF Download
Download 813N252DI-02 Datasheet


813N252DI-02 Datasheet
Jitter Attenuator & FemtoClock NG®
Multiplier
813N252DI-02
DATA SHEET
General Description
Features
The 813N252DI-02 device uses IDT's fourth generation
FemtoClock® NG technology for optimal high clock frequency and
low phase noise performance, combined with a low power
consumption and high power supply noise rejection. The
813N252DI-02 is a PLL based synchronous multiplier that is
optimized for PDH or SONET to Ethernet clock jitter attenuation and
frequency translation.
The813N252DI-02 is a fully integrated Phase Locked loop utilizing a
FemtoClock NG Digital VCXO that provides the low jitter, high
frequency SONET/PDH output clock that easily meets OC-48 jitter
requirements. This VCXO technology simplifies PLL design by
replacing the pullable crystal requirement of analog VCXOs with a
fixed 27MHz generator crystal. Jitter attenuation down to 10Hz is
provided by an external loop filter. Pre-divider and output divider
multiplication ratios are selected using device selection control pins.
The multiplication ratios are optimized to support most common
clock rates used in PDH, SONET and Ethernet applications. The
device requires the use of an external, inexpensive fundamental
mode 27MHz crystal. The device is packaged in a space-saving
32-VFQFN package and supports industrial temperature range.
Pin Assignment
LF1
32 31 30 29 28 27 26 25
1 24
Fourth generation FemtoClock® NG technology
Two LVPECL output pairs
Each output supports independent frequency selection at 25MHz,
125MHz, 156.25MHz and 312.5MHz
Two differential inputs support the following input types: LVPECL,
LVDS, LVHSTL, HCSL
Accepts input frequencies from 8kHz to 155.52MHz including
8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz,
125MHz and 155.52MHz
Crystal interface optimized for a 27MHz, 10pF parallel resonant
crystal
Attenuates the phase jitter of the input clock by using a low-cost
fundamental mode crystal
Customized settings for jitter attenuation and reference tracking
using an external loop filter connection
FemtoClock NG frequency multiplier provides low jitter, high
frequency output
Absolute pull range: ±100ppm
Power supply noise rejection (PSNR): -85dB (typical)
FemtoClock NG VCXO frequency: 2500MHz
RMS phase jitter @ 156.25MHz, using a 27MHz crystal
(12kHz – 20MHz): 0.6ps (typical)
RMS phase jitter @ 125MHz, using a 27MHz crystal
(12kHz – 20MHz): 0.65ps (typical)
3.3V supply voltage
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
VEE
LF0 2
23 nQB
ISET 3
22 QB
VEE
CLK_SEL
4
5
813N252DI-02
21 VCCO
20 nQA
VCC
RESERVED
VEE
6
7
8
9
19
18
17
10 11 12 13 14 15 16
QA
VEE
ODASEL_0
32-pin, 5mm x 5mm VFQFN Package
REVISION 1 08/14/15
1
©2015 INTEGRATED DEVICE TECHNOLOGY, INC.

813N252DI-02 Datasheet
Block Diagram
PDSEL_[2:0]
CLK_SEL
Pullup
Pulldown
CLK0
nCLK0
Pulldown
Pullup /
Pulldown
CLK1
nCLK1
Pulldown
Pullup /
Pulldown
3
0
÷P
1
Phase
Detector
+
Charge
Pump
÷M
813N252DI-02 DATA SHEET
27MHz
Xtal
Osc.
PD
+
LF
DIGITAL
VCXO
FemtoClock NG
VCO
Fractional
Feedback
Divider
A / D Control
Block
2
Pulldown
÷NA
ODASEL_[1:0]
QA
nQA
÷NB
2
Pulldown
QB
nQB
ODBSEL_[1:0]
*** Dashed lines indicates external components
REVISION 1 08/14/15
2 JITTER ATTENUATOR & FEMTOCLOCK NG® MULTIPLIER


Features Datasheet pdf Jitter Attenuator & FemtoClock NG® Mult iplier 813N252DI-02 DATA SHEET Genera l Description Features The 813N252DI- 02 device uses IDT's fourth generation FemtoClock® NG technology for optimal high clock frequency and low phase nois e performance, combined with a low powe r consumption and high power supply noi se rejection. The 813N252DI-02 is a PLL based synchronous multiplier that is o ptimized for PDH or SONET to Ethernet c lock jitter attenuation and frequency t ranslation. The813N252DI-02 is a fully integrated Phase Locked loop utilizing a FemtoClock NG Digital VCXO that provi des the low jitter, high frequency SONE T/PDH output clock that easily meets OC -48 jitter requirements. This VCXO tech nology simplifies PLL design by replaci ng the pullable crystal requirement of analog VCXOs with a fixed 27MHz generat or crystal. Jitter attenuation down to 10Hz is provided by an external loop fi lter. Pre-divider and output divider mu ltiplication ratios are selected using device selection control.
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