HART Modem. AD5700-1 Datasheet

AD5700-1 Modem. Datasheet pdf. Equivalent

Part AD5700-1
Description Low Power HART Modem
Feature Data Sheet Low Power HART Modem AD5700/AD5700-1 FEATURES GENERAL DESCRIPTION HART-compliant full.
Manufacture Analog Devices
Datasheet
Download AD5700-1 Datasheet




AD5700-1
Data Sheet
Low Power HART Modem
AD5700/AD5700-1
FEATURES
GENERAL DESCRIPTION
HART-compliant fully integrated FSK modem
1200 Hz and 2200 Hz sinusoidal shift frequencies
115 µA maximum supply current in receive mode
Suitable for intrinsically safe applications
Integrated receive band-pass filter
Minimal external components required
Clocking optimized for various system configurations
Ultralow power crystal oscillator (60 µA maximum)
External CMOS clock source
Precision internal oscillator (AD5700-1only)
Buffered HART output—extra drive capability
8 kV HBM ESD rating
1.71 V to 5.5 V power supply
1.71 V to 5.5 V interface
−40°C to +125°C operation
4 mm × 4 mm LFCSP package
HART physical layer compliant
UART interface
APPLICATIONS
Field transmitters
HART multiplexers
PLC and DCS analog I/O modules
HART network connectivity
The AD5700/AD5700-1 are single-chip solutions, designed
and specified to operate as a HART® FSK half-duplex modem,
complying with the HART physical layer requirements. The
AD5700/AD5700-1 integrateall of the necessary filtering, signal
detection, modulating, demodulating and signal generation
functions, thus requiring few external components. The 0.5%
precision internal oscillator on the AD5700-1 greatly reduces
the board space requirements, making it ideal for line-powered
applications in both master and slave configurations. The maxi-
mum supply current consumption is 115 µA, making the AD5700/
AD5700-1 an optimal choicefor lowpower loop-powered applica-
tions. Transmit waveforms are phase continuous 1200 Hz and
2200 Hz sinusoids. The AD5700/AD5700-1 contain accurate
carrier detect circuitry and use a standard UART interface.
Table 1. Related Products
Part No. Description
AD5755-1 Quad-channel, 16-bit, serial input, 4 mA to20 mA and
voltage output DAC, dynamic power control, HART
connectivity
AD5421 16-bit, serial input, loop powered, 4 mA to 20 mA DAC
AD5410/ Single-channel, 12-bit/16-bit, serial input, 4 mA to 20 mA
AD5420 current source DACs
AD5412/ Single-channel, 12-bit/16-bit, serial input, current
AD5422 source and voltage output DACs
FUNCTIONAL BLOCK DIAGRAM
REG_CAP
CLKOUT XTAL1 XTAL2 XTAL_EN
VCC
IOVCC
DUPLEX
CD
RXD
TXD
RTS
OSC
FSK
MODULATOR
FSK
DEMODULATOR
AD5700/AD5700-1
DAC
BUFFER
ADC
BAND-PASS
FILTER AND
BIASING
HART_OUT
ADC_IP
HART_IN
CLK_CFG0
CLK_CFG1
VOLTAGE
REFERENCE
RESET
DGND
REF REF_EN
Figure 1.
AGND
FILTER_SEL
Rev. G
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AD5700-1
AD5700/AD5700-1
TABLE OF CONTENTS
Features .....................................................................................1
Applications...............................................................................1
General Description ..................................................................1
Functional Block Diagram.........................................................1
Revision History ........................................................................2
Specifications.............................................................................3
Timing Characteristics...........................................................5
Absolute Maximum Ratings......................................................6
Thermal Resistance................................................................6
ESD Caution ..........................................................................6
Pin Configuration and Function Descriptions...........................7
Typical Performance Characteristics .........................................9
Terminology ............................................................................12
Theory of Operation................................................................13
REVISION HISTORY
12/2016—Rev. F to Rev. G
Changes to Figure 2 and Table 6................................................7
1/2014—Rev. E to Rev. F
Changes to Figure 3 to Figure 7.................................................9
Changes to Example Section....................................................14
10/2013—Rev. D to Rev. E
Changes to t7 and t8 Descriptions, Table 3..................................5
Changed θJA from 30°C/W to 56°C/W.......................................6
Added Figure 13 and Figure 14................................................10
Changes to External Crystal Section and Figure 25.................15
5/2013—Rev. C to Rev. D
2/2013—Rev. B to Rev. C
Changed 2 V to 5.5 V Power Supply to 1.71 V to 5.5 V Power
Supply, Features Section ............................................................1
Changes to Summary Statement, VCC Parameter, and Internal
Reference Voltage Parameter Test Conditions/Comments,
Table 2 .......................................................................................3
Changed VCC = 2 V to 5.5 V to VCC = 1.71 V to 5.5 V in the
Summary Statement, Table 3 .....................................................5
Changes to Pin 18 Description and EPAD Mnemonic and
Description, Table 6...................................................................7
Changes to Figure 9 and Figure 13 ..........................................10
Changes to Figure 28 ...............................................................18
Change to Figure 30.................................................................20
Data Sheet
FSK Modulator.................................................................... 13
Connecting to HART_OUT................................................ 14
FSK Demodulator................................................................ 14
Connecting to HART_IN or ADC_IP ................................. 14
Clock Configuration............................................................ 15
Supply Current Calculations................................................ 16
Power-Down Mode ............................................................. 16
Full Duplex Operation......................................................... 16
Applications Information ........................................................ 17
Supply Decoupling............................................................... 17
Transient Voltage Protection................................................ 17
Typical Connection Diagrams............................................. 18
Outline Dimensions................................................................ 21
Ordering Guide ................................................................... 21
7/2012—Rev. A to Rev. B
Removed VCC and IOVCC Current Consumption Text, Table 2.. 3
Added Internal Oscillator and External Clock Parameters
to Table 2................................................................................... 4
Changes to t2 Description and Endnote 2, Table 3..................... 5
Changes to IOVCC Description, Table 6..................................... 7
Added Supply Current Calculations Section ........................... 16
Added Transient Voltage Protection Section, Figure 26, and
Figure 27; Renumbered Sequentially....................................... 17
Changes to Typical Connection Diagrams Section.................. 18
Changes to Figure 29............................................................... 19
Changes to Figure 30............................................................... 20
Updated Outline Dimensions.................................................. 21
4/2012—Rev. 0 to Rev. A
Change to Transmit Impedance Parameter, RTS Low, Table 2 .. 4
Changes to Figure 3, Figure 4, Figure 5, and Figure 7................ 9
Changes to Figure 10 and Figure 11 ........................................ 10
Changed AD5755 to AD5755-1 Throughout .......................... 17
Change to Figure 27 ................................................................ 18
2/2012—Revision 0: Initial Version
Rev. G | Page 2 of 24







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