Recovery Device. 894D115I-01 Datasheet

894D115I-01 Device. Datasheet pdf. Equivalent

Part 894D115I-01
Description OC-12/STM-4 and OC-3/STM-1 Clock/Data Recovery Device
Feature OC-12/STM-4 and OC-3/STM-1 Clock/Data Recovery Device 894D115I-01 DATA SHEET General Description T.
Manufacture IDT
Datasheet
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894D115I-01
OC-12/STM-4 and OC-3/STM-1
Clock/Data Recovery Device
894D115I-01
DATA SHEET
General Description
The 894D115I-01 is a clock and data recovery circuit. The device
is designed to extract the clock signal from a NRZ-coded STM-4
(OC-12/STS-12) or STM-1 (OC-3/STS-3) input data signal. The
output signals of the device are the recovered clock and retimed
data signals. Input and output are differential signals for best
signal integrity and to support high clock and data rates. All control
inputs and outputs are single-ended signals. An internal PLL is
used for clock generation and recovery. An external clock input is
provided to establish an initial operating frequency of the clock
recovery PLL and to provide a clock reference in the absence of
serial input data. The device supports a signal detect input and a
lock detect output. A bypass circuit is provided to facilitate factory
tests.
Features
Clock recovery for STM-4 (OC-12/STS-12) and
STM-1 (OC-3/STS-3)
Input: NRZ data (622.08 or 155.52 Mbit/s)
Output: clock signal (622.08MHz or 155.52MHz) and retimed
data signal at 622.08 or 155.52 Mbit/s
Internal PLL for clock generation and clock recovery
Differential inputs can accept LVPECL levels
Differential LVPECL data and clock outputs
Lock reference input and PLL lock output
19.44MHz reference clock input
Full 3.3V supply mode
-40°C to 85°C operating temperature
Available in lead-free (RoHS 6) package
See ICS894D115I for a clock/data recovery circuit with a
TSSOP EPAD package
See ICS894D115I-04 for a clock/data recovery circuit with
LVDS outputs
Block Diagram
CAP
nCAP
DATA_IN Pulldown
nDATA_IN Pullup/Pulldown
REF_CLK Pulldown
STS12 Pulldown
SD Pulldown
LOCK_REFN Pullup
BYPASS Pulldown
PLL
0
1
DATA_OUT
nDATA_OUT
CLK_OUT
nCLK_OUT
LOCK_DET
Pin Assignment
VCCA
DATA_IN
nDATA_IN
VEE_PLL
LOCK_DET
STS12
REF_CLK
LOCK_REFN
VEE
VCC
1
2
3
4
5
6
7
8
9
10
20 VCCA
19 VEE_PLL
18 CAP
17 nCAP
16 BYPASS
15 SD
14 DATA_OUT
13 nDATA_OUT
12 CLK_OUT
11 nCLK_OUT
894D115I-01
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
G Package
Top View
894D115I-01 Rev C 2/19/15
1 ©2015 Integrated Device Technology, Inc.



894D115I-01
894D115I-01 DATA SHEET
Functional Description
The 894D115I-01 is designed to extract the clock from a
NRZ-coded STM-4 (OC-12/STS-12) or STM-1 (OC-3/STS-3) input
data signal. The output signals are the recovered clock and retimed
data signal. The device contains an integrated PLL for clock
generation and to lock the output clock to the input data stream.
The PLL attempts to lock to the reference clock input (REF_CLK)
in absence of the serial data stream or if it is forced to by the control
inputs LOCK_REFN or SD. The output clock frequency is
controlled by the STS12 input. The output frequency is 622.08MHz
in STM-4/OC-12/STS-12 mode and 155.52MHz in
STM-1/OC-3/STS-3 mode.
The 894D115I-01 will maintain an output (CLK_OUT/ nCLK_OUT)
frequency deviation of less than ±500ppm with respect to the
REF_CLK reference frequency in a loss of signal state (LOS).
During the LOS state, DATA_OUT is held at logic LOW state and
nDATA_OUT is held at logic HIGH state. An LOS state of the
894D115I-01 is given when BYPASS is set to the logic LOW state
and either one of the SD or LOCK_REFN inputs are at a logic LOW
state. This will enable the use of the SD (signal detect) and the
LOCK_REFN (lock-to-reference) inputs to accept loss of signal
status information from electro-optical receivers. Please refer to
Figure 1, “Signal Detect/PLL Bypass Operation Control Diagram”,
for details.
The lock detect output (LOCK_DET) can be used to monitor the
operating state of the clock/data recovery circuit. LOCK_DET is set
to logic LOW level when the internal oscillator of the PLL and the
reference clock (REF_CLK) deviate from each other by more than
500ppm, or when the CDR is forced to lock the REF_CLK input by
the LOCK_REFN or SD control input. LOCK_DET is set to HIGH
when the PLL is locked to the input data stream and indicates valid
clock and data output signals.
The BYPASS pin should be set to logic LOW state in all
applications. BYPASS set to logic HIGH state is used during
factory test. In BYPASS mode (BYPASS and STS12 are at logic
HIGH state), the internal PLL is bypassed and the inverted
REF_CLK input signal is output at CLK_OUT/nCLK_OUT.
DATA_IN Pulldown
nDATA_IN Pullup/Pulldown
PLL Clock
(on-chip)
REF_CLK Pulldown
STS12 Pulldown
BYPASS Pulldown
0
1
DATA_OUT
nDATA_OUT
CLK_OUT
nCLK_OUT
LOCK_REFN Pullup
SD Pulldown
LOS
(on-chip)
Figure 1. Signal Detect/PLL BYPASS Operation Control Diagram
OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE
2
Rev C 2/19/15





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