VSC8115

VSC8115 Datasheet STS-12/STS-3 Multirate Clock and Data Recovery Unit FEATURES ● Performs clock and data recovery for 622.08 Mbps (STS-12/OC-12/STM-4) or 155.52 Mbps (STS-3/OC-3/STM-1) NRZ data ● 19.44 MHz reference frequency LVTTL input ● Lock Detect output pin monitors data run length and frequency drift from reference clock ● Data is retimed at the output ● Active HIGH Signal Detect LVPECL input ● Low jitter, high-speed outputs support LVPECL and low-power LVDS ● Low power: 188 mW typical ● 3.3 V power supply ● 20-pin TSSOP package ● Requires one external capacitor ● PLL bypass operation facilitates board debug process GENERAL DESCRIPTION The VSC8115 functions as a clock and data recovery (CDR) unit for SONET/SDH-based equipment to derive highspeed timing signals. The VSC8115 recovers the clock from the scrambled non-return to zero (NRZ) data operating at 622.08 Mbps (STS-12/OC-12/STM-4) or 155.52 Mbps (STS-3/OC-3/STM-1). After the clock is recovered, the data is retimed using an output flip-flop. Both recovered clock and retimed data outputs support LVDS and LVPECL signals to facilitate a low-jitter and low-power interface. VSC8115 Block Diagram STS12 BYPASS DATAIN± SD LOCKREFN REFCLK Divider Phase/ Frequency 2 Detector CAP+ CAP– Loop Filter 0 1 VCO 2 LOCKDET DATAOUT± 2 CLKOUT± G52272 Revision 4.4 October 6, 2005 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA 93012 Tel: (800) VITESSE FAX: (805) 987-5896 E-mail: prodinfo@vitesse.com...