Recovery Unit. VSC8115 Datasheet
STS-12/STS-3 Multirate Clock and Data Recovery Unit
● Performs clock and data recovery for
622.08 Mbps (STS-12/OC-12/STM-4) or
155.52 Mbps (STS-3/OC-3/STM-1) NRZ data
● 19.44 MHz reference frequency LVTTL input
● Lock Detect output pin monitors data run length
and frequency drift from reference clock
● Data is retimed at the output
● Active HIGH Signal Detect LVPECL input
● Low jitter, high-speed outputs support LVPECL
and low-power LVDS
● Low power: 188 mW typical
● 3.3 V power supply
● 20-pin TSSOP package
● Requires one external capacitor
● PLL bypass operation facilitates board debug
The VSC8115 functions as a clock and data recovery (CDR) unit for SONET/SDH-based equipment to derive high-
speed timing signals. The VSC8115 recovers the clock from the scrambled non-return to zero (NRZ) data operating at
622.08 Mbps (STS-12/OC-12/STM-4) or 155.52 Mbps (STS-3/OC-3/STM-1). After the clock is recovered, the data
is retimed using an output flip-flop. Both recovered clock and retimed data outputs support LVDS and LVPECL
signals to facilitate a low-jitter and low-power interface.
VSC8115 Block Diagram
G52272 Revision 4.4
October 6, 2005
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The VSC8115 contains an on-chip phase locked-loop (PLL) consisting of a phase/frequency detector (PFD), a loop
filter using one external capacitor, an LC-based voltage-controlled oscillator (VCO), and a programmable frequency
divider. The PFD compares the phase relationship between the VCO output and an external 19.44 MHz LVTTL
reference clock to make coarse adjustments to the VCO block so that its output is held within ±500 ppm of the
reference clock. The PFD also compares the phase relationship between the VCO output and the serial data input to
make fine adjustments to the VCO block. The loop filter converts the phase detector output into a smooth DC voltage.
This DC voltage is used as the input to the VCO block whose output frequency is a function of the input voltage. The
VCO output signal is fed into a programmable frequency divider that generates either a 622.08 Mbps signal if STS12
is HIGH, or a 155.52 Mbps signal if STS12 is LOW, back to the PFD.
The VSC8115 features a lock detection for the PLL. The lock detect (LOCKDET) output goes HIGH to indicate that
the PLL is locked to the serial data inputs and that valid data and clock are present at the high-speed differential
outputs. If LOCKDET output is LOW, then either the PLL is forced to lock to the REFCLK input or the VCO has
drifted away from the local reference clock by more than 500 ppm.
LOCKDET requires that the reference clock be present to operate properly.
The VSC8115 has a signal detect (SD) input and a lock-to-reference (LOCKREFN) input. The SD pin is a LVPECL
input and the LOCKREFN pin is a LVTTL input. These two control pins are used to indicate an LOS condition and
are connected inside the part as shown in Figure 1 on page 3. If either one of these two inputs goes LOW and
BYPASS is LOW, the VSC8115 will enter a Loss of Signal (LOS) state, and will hold the DATAOUT± output at logic
LOW state. During the LOS state, the VSC8115 will also hold the output clock CLKOUT± to within ±500 ppm of the
REFCLK. See Table 1 on page 3.
Most optical modules have an SD output. This SD output indicates that there is sufficient optical power and is
typically active HIGH. If the SD output on the optical module is LVPECL, it should be connected directly to the SD
input on the VSC8115, and the LOCKREFN input be tied HIGH. If the SD output is LVTTL, it should be connected
directly to the LOCKREFN input, and the SD input should be tied HIGH.
The SD and LOCKREFN inputs also can be used for other applications when it is required to hold the CLKOUT±
output to within ±500 ppm of the reference clock and to force the DATAOUT± output to the logic LOW state.
Upon powering up the VSC8115, it is recommended that the reference clock be present at least 40 bit times before the
data signal is introduced.
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G52272 Revision 4.4
October 6, 2005