2 SDRAM. EM44CM1688LBB Datasheet

EM44CM1688LBB SDRAM. Datasheet pdf. Equivalent

Part EM44CM1688LBB
Description 1Gb Double DATA RATE 2 SDRAM
Feature Revision History Revision 0.1 (Nov. 2010) -First release. EM44CM1688LBB Nov. 2010 1/29 www.eorex.
Manufacture Eorex
Download EM44CM1688LBB Datasheet

Revision History Revision 0.1 (Nov. 2010) -First release. E EM44CM1688LBB Datasheet
Recommendation Recommendation Datasheet EM44CM1688LBB Datasheet

Revision History
Revision 0.1 (Nov. 2010)
-First release.
Nov. 2010

1Gb (8M×8Bank×16) Double DATA RATE 2 SDRAM
• JEDEC Standard VDD/VDDQ = 1.8V±0.1V.
• All inputs and outputs are compatible with SSTL_18
• Fully differential clock inputs (CK, /CK) operation.
• Eight Banks
• Posted CAS
• Bust length: 4 and 8.
• Programmable CAS Latency (CL): 5
• Programmable Additive Latency (AL): 0, 1, 2, 3, 4,
5 & 6.
• Write Latency (WL) =Read Latency (RL) -1.
• Read Latency (RL) = Programmable Additive
Latency (AL) + CAS Latency (CL)
• Bi-directional Differential Data Strobe (DQS).
• Data inputs on DQS centers when write.
• Data outputs on DQS, /DQS edges when read.
• On chip DLL align DQ, DQS and /DQS transition
with CK transition.
• DM mask write data-in at the both rising and falling
edges of the data strobe.
• Sequential & Interleaved Burst type available.
• Off-Chip Driver (OCD) Impedance Adjustment
• On Die Termination (ODT)
• Auto Refresh and Self Refresh
• 8,192 Refresh Cycles / 64ms
• Average Refresh Period 7.8us at lower than Tcase 85
°C, 3.9us at 85°C < Tcase 95°C
• RoHS Compliance
• Partial Array Self-Refresh (PASR)
• High Temperature Self-Refresh rate enable
The EM44CM1688LBB is a high speed Double Date
Rate 2 (DDR2) Synchronous DRAM fabricated with
ultra high performance CMOS process containing
1,073,741,824 bits which organized as 8Mbits x 8
banks by 16 bits. This synchronous device achieves
high speed double-data-rate transfer rates of up to
800 Mb/sec/pin (DDR2-800) for general applications.
The chip is designed to comply with the following key
DDR2 SDRAM features: (1) posted CAS with
additive latency, (2) write latency = read latency -1,
(3) Off-Chip Driver (OCD) impedance adjustment and
On Die Termination (4) normal and weak strength
data output driver. All of the control and address
inputs are synchronized with a pair of externally
supplied differential clocks. Inputs are latched at the
cross point of differential clocks (CK rising and /CK
falling). All I/Os are synchronized with a pair of
bidirectional strobes (DQS and /DQS) in a source
synchronous fashion. The address bus is used to
convey row, column and bank address information in
a /RAS and /CAS multiplexing style. The 1Gb DDR2
device operates with a single power supply: 1.8V ±
0.1V VDD and VDDQ. Available package:
TFBGA-84Ball (with 0.8mm x 0.8mm ball pitch)
Nov. 2010

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