Document
Revision History
Revision 0.1 (Oct. 2013) -First release.
EM47EM1688MBB
Oct. 2013
1/38
www.eorex.com
EM47EM1688MBB
4Gb (32M×8Bank×16) Double DATA RATE 3 SDRAM
Features
• JEDEC Standard VDD/VDDQ = 1.35V-0.065/+0.1V
• Backward compatible to VDD/ VDDQ = 1.5V ±0.075V..
• All inputs and outputs are compatible with SSTL_15
interface. • Fully differential clock inputs (CK, /CK) operation. • Eight Banks • Posted CAS by programmable additive latency • Bust length: 4 with Burst Chop (BC) and 8. • CAS Write Latency (CWL): 5,6,7,8 • CAS Latency (CL): 6,7,8,9,10,11 • Write Latency (WL) =Read Latency (RL) -1. • Bi-directional Differential Data Strobe (DQS). • Data inputs on DQS centers when write. • Data outputs on DQS, /DQS edges when read. • On chip DLL align DQ, DQS and /DQS transition
with CK transition. • DM mask write data-in at the both rising and falling
edges of the data strobe. • Sequential & Interleaved Burst type available both
for 8 & 4 with BC. .