3 SDRAM. EM47EM3288MBA Datasheet

EM47EM3288MBA SDRAM. Datasheet pdf. Equivalent

Part EM47EM3288MBA
Description 8Gb Double DATA RATE 3 SDRAM
Feature EM47EM3288MBA 8Gb (32M×8Bank×32) Double DATA RATE 3 Stack SDRAM Features • VDD/VDDQ = 1.35V -0.065/.
Manufacture Eorex
Datasheet
Download EM47EM3288MBA Datasheet

EM47EM3288MBA 8Gb (32M×8Bank×32) Double DATA RATE 3 Stack SD EM47EM3288MBA Datasheet
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EM47EM3288MBA
EM47EM3288MBA
8Gb (32M×8Bank×32) Double DATA RATE 3 Stack SDRAM
Features
VDD/VDDQ = 1.35V -0.065/+0.1V.
Backward compatible to VDD = VDDQ = 1.5V
±0.075V.Supports DDR3L devices to be backward
compatible in 1.5V applications.
Fully differential clock inputs (CK, /CK) operation.
Eight Banks
Posted CAS by programmable additive latency
Bust length: 4 with Burst Chop (BC) and 8.
CAS Write Latency (CWL): 5,6,7,8
CAS Latency (CL): 5,6,7,8,9,10
• Write Latency (WL) =Read Latency (RL) -1.
• Bi-directional Differential Data Strobe (DQS).
• Data inputs on DQS centers when write.
• Data outputs on DQS, /DQS edges when read.
• On chip DLL align DQ, DQS and /DQS transition
with CK transition.
• DM mask write data-in at the both rising and falling
edges of the data strobe.
• Sequential & Interleaved Burst type available both
for 8 & 4 with BC.
Multi Purpose Register (MPR) for pre-defined
pattern read out
• On Die Termination (ODT) options: Synchronous
ODT, Dynamic ODT, and Asynchronous ODT
• Auto Refresh and Self Refresh
• 8,192 Refresh Cycles / 64ms
Refresh Interval: 7.8us Tcase between 0°C ~ 85°C
Refresh Interval: 3.9us Tcase between 85°C ~ 95°C
• RoHS Compliance
Driver Strength:RZQ/7, RZQ/6 (RZQ=240Ω)
• High Temperature Self-Refresh rate enable
ZQ calibration for DQ drive and ODT
RESET pin for initialization and reset function
Description
The EM47EM3288MBA is a high speed stack
multi-chip package integrated 4Gbits x2 DDR3L
SDRAM and fabricated with ultra high performance
CMOS process containing 8G bits which organized
as 32Mbits x 8 banks by 32 bits. This synchronous
device achieves high speed double-data-rate transfer
rates of up to 1600 Mb/sec/pin (DDR3L-1600) for
general applications. The chip is designed to comply
with the following key DDR3L SDRAM features: (1)
posted CAS with additive latency, (2) write latency =
read latency -1, (3) On Die Termination (4)
programmable driver strength data,(5) seamless BL4
access. All of the control and address inputs are
synchronized with a pair of externally supplied
differential clocks. Inputs are latched at the cross
point of differential clocks (CK rising and /CK falling).
All I/Os are synchronized with a pair of bidirectional
differential data strobes (DQS and /DQS) in a source
synchronous fashion. The address bus is used to
convey row, column and bank address information in
a /RAS and /CAS multiplexing style. The 8Gb DDR3L
devices operates with a single power supply: 1.35V
±1.35V -0.065/+0.1V or 1.5V ± 0.075V VDD and
VDDQ. Available package with RoHS compliance:
FBGA-136Ball (14 x 12 x 1.4 mm)
Apr. 2014
1/39
www.eorex.com



EM47EM3288MBA
EM47EM3288MBA
Ordering Information
Part No
EM47EM3288MBA-150
Organization Max. Freq
256M X 32 DDR3L-1333H (9-9-9)
EM47EM3288MBA-125
256M X 32 DDR3L-1600K (11-11-11)
Note: Speed ( tCK *) is in order of CL-tRCD-tRP
Package
FBGA-136B
FBGA-136B
Grade
Commercial
Commercial
Ball Assignment: Top View
1234
9
VDD
VSS
VSSQ
DQ1
A
DQ9
VDDQ
DQ0
VSSQ
DQ3
B DQ11
VDDQ
DQ2
VSSQ
DM0
C
DM1
VSSQ
VDDQ
DQS0
/DQS0
D
/DQS1
VSSQ
DQ4
VDDQ
DQ5
E DQ13
VSS
DQ6
VDDQ
DQ7
F DQ15
VDD
NC
CAS
RAS
G
CK
RESET
BA2
ODT
CS
H A10
VREFDQ
VSS
ZQ0
WE
J
A1
BA0
A9
A2
A0
K A4
VDD
A7
A5
A3
L
A8
VSS
DQ24
VDDQ
DQ25
M
DQ17
VSSQ
DQ26
VDDQ
DQ27
N
DQ19
VSSQ
VDDQ
DQS3
/DQS3
P
/DQS2
VDDQ
DQ28
VSSQ
DM3
R
DM2
VDDQ
DQ30
VSSQ
DQ29
T
DQ21
VDD
VSS
VSSQ
DQ31
U
DQ23
136 Ball FBGA
10
VSSQ
VSSQ
VSSQ
DQS1
VDDQ
VDDQ
CK
A14
ZQ1
A6
A11
VDDQ
VDDQ
DQS2
VSSQ
VSSQ
VSSQ
11
VSS
DQ8
DQ10
VDDQ
DQ12
DQ14
CKE
NC
VSS
A12/ BC
A13
DQ16
DQ18
VDDQ
DQ20
DQ22
VSS
12
VDD
VDDQ
VDDQ
VSSQ
VSSQ
VSS
VDD
NC
VREFCA
BA1
VDD
VSS
VSSQ
VSSQ
VDDQ
VDDQ
VDD
Apr. 2014
2/39
www.eorex.com





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