Document
eorex
Revision History
Revision 0.1 (Dec. 2013) - First release
EM488M3244VBD
Dec. 2013
www.eorex.com 1/18
eorex
EM488M3244VBD
256Mb (2M4Bank32) Synchronous DRAM
Features
• Fully Synchronous to Positive Clock Edge • Single 3.3V 0.3V Power Supply • LVTTL Compatible with Multiplexed Address • Programmable Burst Length (B/L) - 1, 2, 4, 8
or Full Page • Programmable CAS Latency (C/L) - 2 or 3 • Data Mask (DQM) for Read / Write Masking • Programmable Wrap Sequence
– Sequential (B/L = 1/2/4/8/full Page) – Interleave (B/L = 1/2/4/8) • Burst Read with Single-bit Write Operation • All Inputs are Sampled at the Rising Edge of
the System Clock • Auto Refresh and Self Refresh • 4,096 Refresh Cycles / 64ms (15.625us)
Description
The EM488M3244VBD is Synchronous Dynamic Random Access Memory (SDRAM) organized as 2Meg words x 4 banks by 32 bits. All inputs and outputs are synchronized with the positive edge of the clock. The 256Mb SDRAM uses synchronized pipe.