Synchronous DRAM. EM48AM1684VTC Datasheet

EM48AM1684VTC DRAM. Datasheet pdf. Equivalent

Part EM48AM1684VTC
Description 256Mb Synchronous DRAM
Feature eorex Revision History Revision 0.1 (Aug. 2007) - First release. Revision 0.2 (Jan. 2009).. - modify.
Manufacture Eorex
Datasheet
Download EM48AM1684VTC Datasheet

eorex Revision History Revision 0.1 (Aug. 2007) - First rele EM48AM1684VTC Datasheet
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EM48AM1684VTC
eorex
Revision History
Revision 0.1 (Aug. 2007)
- First release.
Revision 0.2 (Jan. 2009)..
- modify improved ICCs
EM48AM1684VTC
Jan. 2009
www.eorex.com
1/18



EM48AM1684VTC
eorex
EM48AM1684VTC
256Mb (4M×4Bank×16) Synchronous DRAM
Features
• Fully Synchronous to Positive Clock Edge
• Single 3.3V ±0.3V Power Supply
• LVTTL Compatible with Multiplexed Address
• Programmable Burst Length (B/L) - 1, 2, 4, 8
or Full Page
• Programmable CAS Latency (C/L) - 2 or 3
• Data Mask (DQM) for Read / Write Masking
• Programmable Wrap Sequence
– Sequential (B/L = 1/2/4/8/full Page)
– Interleave (B/L = 1/2/4/8)
• Burst Read with Single-bit Write Operation
• All Inputs are Sampled at the Rising Edge of
the System Clock
• Auto Refresh and Self Refresh
• 8,192 Refresh Cycles / 64ms (7.8us)
Ordering Information
Description
The EM48AM1684VTC is Synchronous Dynamic
Random Access Memory (SDRAM) organized as
4Meg words x 4 banks by 16 bits. All inputs and
outputs are synchronized with the positive edge of
the clock.
The 256Mb SDRAM uses synchronized pipelined
architecture to achieve high speed data transfer
rates and is designed to operate at 3.3V low power
memory system. It also provides auto refresh with
power saving / down mode. All inputs and outputs
voltage levels are compatible with LVTTL.
Available packages: TSOPII 54P 400mil.
Part No
EM48AM1684VTC-75F
EM48AM1684VTC-7F
Organization
16M X 16
16M X 16
Max. Freq
133MHz @CL3
143MHz @CL3
Package
54pin TSOP(ll)
54pin TSOP(ll)
Grade
Commercial
Commercial
Pb
Free
Free
* EOREX reserves the right to change products or specification without notice.
Jan. 2009
www.eorex.com
2/18





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