Synchronous DRAM. EM48BM0884VTA Datasheet

EM48BM0884VTA DRAM. Datasheet pdf. Equivalent

Part EM48BM0884VTA
Description 256Mb Synchronous DRAM
Feature Revision History Revision 0.1 (Aug. 2011) - First release. EM48BM0884VTA Aug. 2011 1/20 www.eore.
Manufacture Eorex
Datasheet
Download EM48BM0884VTA Datasheet

Revision History Revision 0.1 (Aug. 2011) - First release. EM48BM0884VTA Datasheet
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EM48BM0884VTA
Revision History
Revision 0.1 (Aug. 2011)
- First release.
EM48BM0884VTA
Aug. 2011
1/20
www.eorex.com



EM48BM0884VTA
EM48BM0884VTA
256Mb (8M×4Bank×8) Synchronous DRAM
Features
Description
• Fully Synchronous to Positive Clock Edge
• Single 3.3V ±0.3V Power Supply
• LVTTL Compatible with Multiplexed Address
• Programmable Burst Length (B/L) - 1, 2, 4, 8
or Full Page
• Programmable CAS Latency (C/L) - 3
• Data Mask (DQM) for Read / Write Masking
• Programmable Wrap Sequence
– Sequential (B/L = 1/2/4/8/full Page)
– Interleave (B/L = 1/2/4/8)
• Burst Read with Single-bit Write Operation
• All Inputs are sampled at the Rising Edge of
the System Clock
• Auto Refresh and Self Refresh
• 8,192 Refresh Cycles / 64ms
The EM48BM0884VTA is Synchronous Dynamic
Random Access Memory (SDRAM) organized
as 8Meg words x 4 banks by 8 bits. All inputs
and outputs are synchronized with the positive
edge of the clock.
The 256Mb SDRAM uses synchronized
pipelined architecture to achieve high speed
data transfer rates and is designed to operate at
3.3V low power memory system. It also provides
auto refresh with power saving / down mode. All
inputs and outputs voltage levels are compatible
with LVTTL.
Available packages: TSOPII 54P 400mil.
Ordering Information
Part No
EM48BM0884VTA-6F
EM48BM0884VTA-7F
Organization Max. Freq
32M X 8
166MHz @CL3
32M X 8
143MHz @CL3
Package
54pin TSOP(ll)
54pin TSOP(ll)
Grade
Commercial
Commercial
Pb
Free
Free
Aug. 2011
2/20
www.eorex.com





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