AND Gate. MC74HCT08A Datasheet

MC74HCT08A Gate. Datasheet pdf. Equivalent

Part MC74HCT08A
Description Quad 2-Input AND Gate
Feature MC74HCT08A Quad 2-Input AND Gate with LSTTL Compatible Inputs High−Performance Silicon−Gate CMOS T.
Manufacture ON Semiconductor
Datasheet
Download MC74HCT08A Datasheet

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Quad 2-Input AND Gat MC74HCT08A Datasheet
MC74HCT08A Quad 2-Input AND Gate with LSTTL Compatible Inpu MC74HCT08A Datasheet
Recommendation Recommendation Datasheet MC74HCT08A Datasheet





MC74HCT08A
MC74HCT08A
Quad 2-Input AND Gate
with LSTTL Compatible
Inputs
HighPerformance SiliconGate CMOS
The MC74HCT08A is identical in pinout to the LS08. The device
inputs are compatible with Standard CMOS or LSTTL outputs.
Features
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 V to 6.0 V
Low Input Current: 1 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7A Requirements
Chip Complexity: 24 FETs or 6 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ100
Qualified and PPAP Capable
These are PbFree Devices
A1 1
B1 2
3 Y1
A2 4
B2 5
A3 9
B3 10
6 Y2
Y = AB
8 Y3
A4 12
B4 13
11 Y4
PIN 14 = VCC
PIN 7 = GND
Figure 1. Logic Diagram
Pinout: 14Lead Packages (Top View)
VCC B4 A4 Y4 B3 A3 Y3
14 13 12 11 10 9 8
14
1
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MARKING
DIAGRAMS
14
SOIC14
D SUFFIX
CASE 751A
1
HCT08AG
AWLYWW
14
14
TSSOP14
DT SUFFIX
1 CASE 948G
HCT
08
ALYW G
G
1
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = PbFree Package
(Note: Microdot may be in either location)
FUNCTION TABLE
Inputs
Output
AB
Y
LL
LH
HL
HH
L
L
L
H
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
1234567
A1 B1 Y1 A2 B2 Y2 GND
Figure 2. Pinout
© Semiconductor Components Industries, LLC, 2014
February, 2014 Rev. 9
1
Publication Order Number:
MC74HCT08A/D



MC74HCT08A
MC74HCT08A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC DC Supply Voltage (Referenced to GND)
0.5 to +7.0
V
Vin DC Input Voltage (Referenced to GND)
0.5 to VCC +0.5
V
Vout DC Output Voltage (Referenced to GND)
0.5 to VCC +0.5
V
Iin DC Input Current, per Pin
±20 mA
Iout DC Output Current, per Pin
±25 mA
ICC DC Supply Current, VCC and GND Pins
±50 mA
PD
Power Dissipation in Still Air,
SOIC Package
TSSOP Package
500
450
mW
Tstg Storage Temperature
TL Lead Temperature, 1 mm from Case for 10 Seconds
SOIC or TSSOP Package
65 to +150
260
°C
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating SOIC Package: 7 mW/°C from 65°C to 125°C
TSSOP Package: 6.1 mW/°C from 65°C to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
Vin, Vout
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage
(Referenced to GND)
TA Operating Temperature, All Package Types
tr, tf Input Rise and Fall Time
(Figure 3)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
Min Max Unit
2.0 6.0 V
0
VCC
V
55
+125
°C
0
1000
ns
0 500
0 400
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