Flash Memory. SST26VF064BA Datasheet

SST26VF064BA Memory. Datasheet pdf. Equivalent

Part SST26VF064BA
Description 2.5V/3.0V 64 Mbit Serial Quad I/O (SQI) Flash Memory
Feature SST26VF064B / SST26VF064BA 2.5V/3.0V 64 Mbit Serial Quad I/O (SQI) Flash Memory Features • Single .
Manufacture Microchip
Datasheet
Download SST26VF064BA Datasheet

SST26VF064B / SST26VF064BA 2.5V/3.0V 64 Mbit Serial Quad I/ SST26VF064BA Datasheet
Recommendation Recommendation Datasheet SST26VF064BA Datasheet





SST26VF064BA
SST26VF064B / SST26VF064BA
2.5V/3.0V 64 Mbit Serial Quad I/O (SQI) Flash Memory
Features
• Single Voltage Read and Write Operations
- 2.7-3.6V or 2.3-3.6V
• Serial Interface Architecture
- Nibble-wide multiplexed I/O’s with SPI-like serial
command structure
- Mode 0 and Mode 3
- x1/x2/x4 Serial Peripheral Interface (SPI) Protocol
• High Speed Clock Frequency
- 2.7-3.6V: 104 MHz max
- 2.3-3.6V: 80 MHz max
• Burst Modes
- Continuous linear burst
- 8/16/32/64 Byte linear burst with wrap-around
• Superior Reliability
- Endurance: 100,000 Cycles (min)
- Greater than 100 years Data Retention
• Low Power Consumption:
- Active Read current: 15 mA (typical @ 104 MHz)
- Standby Current: 15 µA (typical)
• Fast Erase Time
- Sector/Block Erase: 18 ms (typ), 25ms (max)
- Chip Erase: 35 ms (typ), 50 ms (max)
• Page-Program
- 256 Bytes per page in x1 or x4 mode
• End-of-Write Detection
- Software polling the BUSY bit in status register
• Flexible Erase Capability
- Uniform 4 KByte sectors
- Four 8 KByte top and bottom parameter
overlay blocks
- One 32 KByte top and bottom overlay block
- Uniform 64 KByte overlay blocks
• Write-Suspend
- Suspend Program or Erase operation to access
another block/sector
• Software Reset (RST) mode
• Software Protection
- Individual-Block Write Protection with permanent
lock-down capability
- 64 KByte blocks, two 32 KByte blocks, and
eight 8 KByte parameter blocks
- Read Protection on top and bottom 8 KByte
parameter blocks
• Security ID
- One-Time Programmable (OTP) 2 KByte, Secure ID
- 64 bit unique, factory pre-programmed identifier
- User-programmable area
• Temperature Range
- Industrial: -40°C to +85°C
- Extended: -40°C to +105°C
• Packages Available
- 8-contact WDFN (6mm x 5mm)
- 8-contact WDFN (6mm x 8 mm)
- 8-lead SOIJ (5.28 mm)
- 16-lead SOIC (7.50 mm)
- 24-ball TBGA (6mm x 8mm)
• All devices are RoHS compliant
Product Description
The Serial Quad I/O™ (SQI™) family of flash-memory
devices features a six-wire, 4-bit I/O interface that
allows for low-power, high-performance operation in a
low pin-count package. SST26VF064B/064BA also
support full command-set compatibility to traditional
Serial Peripheral Interface (SPI) protocol. System
designs using SQI flash devices occupy less board
space and ultimately lower system costs.
All members of the 26 Series, SQI family are manufac-
tured with proprietary, high-performance CMOS Super-
Flash® technology. The split-gate cell design and thick-
oxide tunneling injector attain better reliability and man-
ufacturability compared with alternate approaches.
SST26VF064B/064BA significantly improve perfor-
mance and reliability, while lowering power consump-
tion. These devices write (Program or Erase) with a
single power supply of 2.3-3.6V. The total energy con-
sumed is a function of the applied voltage, current, and
time of application. Since for any given voltage range,
the SuperFlash technology uses less current to pro-
gram and has a shorter erase time, the total energy
consumed during any Erase or Program operation is
less than alternative flash memory technologies.
SST26VF064B/064BA are offered in 8-contact WDFN
(6 mm x 5 mm or 6mm x 8mm), 8-lead SOIJ (5.28 mm),
16-lead SOIC (7.50 mm), and 24-ball TBGA. See Fig-
ure 2-2 for pin assignments.
Two configurations are available upon order.
SST26VF064B default at power-up has the WP# and
HOLD# pins enabled, and the SIO2 and SIO3 pins dis-
abled, to initiate SPI-protocol operations.
2015 Microchip Technology Inc.
DS20005119G-page 1



SST26VF064BA
SST26VF064B / SST26VF064BA
SST26VF064BA default at power-up has the WP# and
HOLD# pins disabled, and the SIO2 and SIO3 pins
enabled, to initiate Quad I/O operations. See “I/O Con-
figuration (IOC)” on page 12 for more information about
configuring WP#/HOLD# and SIO3/SIO4 pins
.
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DS20005119G-page 2
2015 Microchip Technology Inc.





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