Synchronous DRAM. EDD1216ALTA Datasheet

EDD1216ALTA DRAM. Datasheet pdf. Equivalent

Part EDD1216ALTA
Description 128 M-bit Synchronous DRAM
Feature PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 128 M-bit Synchr.
Manufacture Elpida Memory
Datasheet
Download EDD1216ALTA Datasheet

PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT EDD1204ALTA, E EDD1216ALTA Datasheet
Recommendation Recommendation Datasheet EDD1216ALTA Datasheet





EDD1216ALTA
PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
128 M-bit Synchronous DRAM with Double Data Rate
(4-bank, SSTL_2)
Description
The EDD1204ALTA, EDD1208ALTA, EDD1216ALTA are high-speed 134,217,728 bits synchronous dynamic
random-access memories, organized as 8,388,608x4x4, 4,194,304x8x4, 2,097,152x16x4 (word x bit x bank),
respectively.
The synchronous DRAMs use Double Data Rate (DDR) where data bandwidth is twice of regular synchronous
DRAM.
The synchronous DRAM is compatible with SSTL_2 (Stub Series terminated Logic for 2.5 V).
The synchronous DRAM is packaged in 66-pin Plastic TSOP (II).
Features
Fully Synchronous Dynamic RAM with all input signals except DM, DQS and DQ referenced to a positive clock edge
Double Data Rate interface
Differential CLK (/CLK) input
Data inputs and DM are synchronized with both edges of DQS
Data outputs and DQS are synchronized with a cross point of CLK and /CLK
Quad internal banks operation
Possible to assert random column address in every clock cycle
Programmable Mode register set
/CAS latency (2, 2.5)
Burst length (2, 4, 8)
Wrap sequence (Sequential / Interleave)
Automatic precharge and controlled precharge
CBR (Auto) refresh and self refresh
x4, x8, x16 organization
Byte write control (x4, x8) by DM
Byte write control (x16) by LDM and UDM
2.5 V ± 0.2 V Power supply for VDD
2.5 V ± 0.2 V Power supply for VDDQ
Maximum clock frequency up to 133 MHz
SSTL_2 compatible with all signals
4,096 refresh cycles/64 ms
66-pin Plastic TSOP (II) (10.16 mm (400))
Burst termination by Precharge command and Burst stop command
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
Document No. E0136E30 (Ver. 3.0)
Date Published October 2001 (K)
Printed in Japan
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.



EDD1216ALTA
Ordering Information
Part Number
EDD1204ALTA-7A
EDD1204ALTA-75
EDD1204ALTA-1A
EDD1208ALTA-7A
EDD1208ALTA-75
EDD1208ALTA-1A
EDD1216ALTA-7A
EDD1216ALTA-75
EDD1216ALTA-1A
EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
Organization
(word x bit x bank)
8M x 4 x 4
4M x 8 x 4
2M x 16 x 4
Clock frequency
MHz (MAX.)
133
133
100
133
133
100
133
133
100
Package
66-pin Plastic TSOP (II)
(10.16 mm (400))
2 Preliminary Data Sheet E0136E30





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