EDD1232AABH

DATA SHEET 128M bits DDR SDRAM EDD1232AABH (4M words × 32 bits) Description The EDD1232AABH is a 128M bits DDR SDRAM organized as 1,048,576 words × 32 bits × 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. It is packaged in 144-ball FBGA package. Features Power supply: VDDQ = 2.5V ± 0.2V : VDD = 2.5V ± 0.2V Data rate: 333Mbps/266Mbps (max.) Double Data Rate architecture; two data transfers per clock cycle Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver Data inputs, outputs, and DM are synchronized with DQS 4 internal banks for concurrent operation DQS is ...