DDR SDRAM. EDD1232ABBH Datasheet

EDD1232ABBH SDRAM. Datasheet pdf. Equivalent

Part EDD1232ABBH
Description 128M bits DDR SDRAM
Feature DATA SHEET 128M bits DDR SDRAM EDD1232ABBH (4M words × 32 bits) Specifications • Density: 128M bi.
Manufacture Elpida Memory
Datasheet
Download EDD1232ABBH Datasheet

DATA SHEET 128M bits DDR SDRAM EDD1232ABBH (4M words × 32 EDD1232ABBH Datasheet
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EDD1232ABBH
DATA SHEET
128M bits DDR SDRAM
EDD1232ABBH (4M words × 32 bits)
Specifications
Density: 128M bits
Organization
1M words × 32 bits × 4 banks
Package: 144-ball FBGA
Lead-free (RoHS compliant)
Power supply: VDD, VDDQ = 2.5V ± 0.125V
Data rate: 400Mbps (max.)
Four internal banks for concurrent operation
Interface: SSTL_2
Burst lengths (BL): 2, 4, 8
Burst type (BT):
Sequential (2, 4, 8)
Interleave (2, 4, 8)
/CAS Latency (CL): 3
Precharge: auto precharge operation for each burst
access
Driver strength: weak/matched
Refresh: auto-refresh, self-refresh
Refresh cycles: 4096 cycles/32ms
Average refresh period: 7.8μs
Operating ambient temperature range
TA = 0°C to +70°C
Features
• ×32 organization
Double-data-rate architecture; two data transfers per
clock cycle
The high-speed data transfer is realized by the 2 bits
prefetch pipelined architecture
Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver
Data inputs, outputs, and DM are synchronized with
DQS
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Document No. E0874E40 (Ver. 4.0)
Date Published April 2007 (K) Japan
Printed in Japan
URL: http://www.elpida.com
©Elpida Memory, Inc. 2006-2007



EDD1232ABBH
EDD1232ABBH
Ordering Information
Part number
EDD1232ABBH-5C-E
Mask
version
B
Organization
(words × bits)
4M × 32
Internal
banks
4
Data Rate
Mbps (max.)
400
JEDEC speed bin
(CL-tRCDRD-tRP)
DDR400C (3-4-4)
Package
144-ball FBGA
Part Number
E D D 12 32 A B BH - 5C - E
Elpida Memory
Type
D: Monolithic Device
Product Family
D: DDR SDRAM
Density / Bank
12: 128M / 4-bank
Organization
32: x32
Power Supply, Interface
A: 2.5V, SSTL_2
Die Rev.
Package
BH: FBGA
Speed
5C: DDR400C (3-4-4)
Environment Code
E: Lead Free
(RoHS compliant)
Data Sheet E0874E40 (Ver. 4.0)
2





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