Static RAM. MCM62996 Datasheet

MCM62996 RAM. Datasheet pdf. Equivalent


Part MCM62996
Description 16K x 16 Bit Asynchronous Fast Static RAM
Feature MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM62996/D 16K x 16 Bit Asynchronous .
Manufacture Motorola
Datasheet
Download MCM62996 Datasheet


MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document b MCM62996 Datasheet
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MCM62996
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM62996/D
16K x 16 Bit Asynchronous
Fast Static RAM
MCM62996
The MCM62996 is a 262,144 bit static random access memory organized as
16,384 words of 16 bits, fabricated using Motorola’s high–performance
silicon–gate CMOS technology. The device integrates a 16K x 16 SRAM core
with active high and active low chip enables, separate upper and lower byte write
strobes, and a fast output enable. This device has increased output drive
capability supported by multiple power pins. In addition, the output levels can be
either 3.3 V or 5 V TTL compatible by choice of the appropriate output bus power
supply.
Dual write strobes (BWL and BWH) are provided to allow individually writeable
bytes. BWL controls DQ0 – DQ7 (the lower bits), while BWH controls DQ8 –
DQ15 (the upper bits).
Additional power supply pins have been utilized and placed on the package for
maximum performance. In addition, the output buffer power pins are electrically
isolated from the other two and supply power only to the output buffers. This
allows connecting the output buffers to 3.3 V instead of 5.0 V if desired. If 3.3 V
output levels are chosen, the output buffer impedance in the “high” state is
approximately equal to the impedance in the “low” state thereby allowing
simplified transmission line terminations.
The MCM62996 will be available in a 52–pin plastic leaded chip carrier PLCC.
This device is ideally suited for systems that require wide data bus widths,
cache memory, and tag RAMs.
Single 5 V ± 10% Power Supply
Choice of 5 V or 3.3 V ± 10% Power Supplies for Output Buffers
Fast Access Times: 12/15/20/25 ns Max
Byte Writeable via Dual Write Strobes with Abort Write Capability
Common Data Inputs and Data Outputs
Output Enable Controlled Three State Outputs
High Output Drive Capability: 85 pF/Output at Rated Access Time
High Board Density 52–Lead PLCC Package
DQ8
DQ9
VCCQ
VSSQ
DQ10
DQ11
DQ12
DQ13
VSSQ
VCCQ
DQ14
DQ15
NC
FN PACKAGE
52–LEAD PLCC
CASE 778–02
PIN ASSIGNMENT
7 6 5 4 3 2 1 52 51 50 49 48 47
8 46
9 45
10 44
11 43
12 42
13 41
14 40
15 39
16 38
17 37
18 36
19 35
20 34
21 22 23 24 25 26 27 28 29 30 31 32 33
NC
DQ7
DQ6
VCCQ
VSSQ
DQ5
DQ4
DQ3
DQ2
VSSQ
VCCQ
DQ1
DQ0
BLOCK DIAGRAM
A0 – A13 14
E
E
MEMORY ARRAY
16K x 16
128 ROWS
128 COLUMNS
16
16
WRITE AMP
CONTROL
OUTPUT DQ0 – DQ15
BUFFER 16
W BWL BWH
G
PIN NAMES
A0 – A13 . . . . . . . . . . . . . . . . Address Inputs
W . . . . . . . . . . . . . . . . . . . . . . . . Write Enable
BWL . . . . . . . . . . . . . Byte Write Strobe Low
BWH . . . . . . . . . . . . Byte Write Strobe High
E . . . . . . . . . . . . . . . Active High Chip Enable
E . . . . . . . . . . . . . . . Active Low Chip Enable
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
DQ0 – DQ15 . . . . . . . . . . Data Input/Output
VCC . . . . . . . . . . . . . . . . + 5 V Power Supply
VCCQ . . . . . . . Output Buffer Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
VSSQ . . . . . . . . . . . . Output Buffer Ground
NC . . . . . . . . . . . . . . . . . . . . . No Connection
All power supply and ground pins must be
connected for proper operation of the device.
VCC VCCQ at all times including power up.
REV 3
5/95
M© OMoTtoOroRla,OInLc.A19F95AST SRAM
MCM62996
1



MCM62996
TRUTH TABLE (See Notes)
E W BWL BWH G
Mode
Supply
I/O
Current Status
FXX XX
Deselected Cycle
ISB High–Z
THX XH
Read Cycle
ICC High–Z
THX X L
Read Cycle
ICC Data Out
TL L
LX
Write Cycle All Bits
ICC High–Z
T L H H X Aborted Write Cycle
ICC High–Z
T
L
L
H
X Write Cycle Lower 8 Bits ICC
High–Z
T
L
H
L
X Write Cycle Upper 8 Bits ICC
High–Z
NOTE: True (T) is E = 1 and E = 0. E, E, and addresses satisfy the specified setup and hold
times for the falling edge of LE. Data–in satisfies the specified setup and hold times
for falling edge of DL.
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = VSSQ = 0 V)
Rating
Symbol
Value
Unit
Power Supply Voltage
VCC
– 0.5 to + 7.0
V
Voltage Relative to VSS/VSSQ for Any Pin Vin, Vout – 0.5 to VCC + 0.5
Except VCC and VCCQ
V
Output Current (per I/O)
Iout ± 20 mA
Power Dissipation
PD 2.0 W
Temperature Under Bias
Tbias
– 10 to + 85
°C
Operating Temperature
TA
0 to + 70
°C
Storage Temperature
Tstg
– 55 to + 125
°C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however, it
is advised that normal precautions be
taken to avoid application of any voltage
higher than maximum rated voltages to this
high impedance circuit.
This CMOS memory circuit has been
designed to meet the dc and ac specifica-
tions shown in the tables, after thermal
equilibrium has been established.
This device contains circuitry that will
ensure the output devices are in High–Z at
power up.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = VCCQ = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = VSSQ = 0 V)
Parameter
Symbol
Min
Typ
Max Unit
Supply Voltage (Operating Voltage Range)
Output Buffer Supply Voltage (5.0 V TTL Compatible)
(3.3 V 50 Compatible)
VCC*
4.5
5.0
5.5 V
VCCQ
4.5
5.0
5.5 V
3.0 3.3 3.6
Input High Voltage
Input Low Voltage
* VIL(min) = – 3.0 V ac (pulse width 20 ns)
VIH 2.2
VIL – 0.5*
VCC + 0.3 V
— 0.8 V
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter
Symbol
Min
Typ
Max Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC)
Output Leakage Current (G = VIH)
AC Supply Current (Iout = 0 mA, All Inputs = VIL or VIH, VIL = 0.0 V and
VIH 3.0 V, Cycle Time tAVAV min)
Ilkg(I)
Ilkg(O)
ICCA12
ICCA15
ICCA20
ICCA25
± 1.0
µA
± 1.0
µA
295 350 mA
275 330
265 320
255 310
Standby Current (E = VIL, E = VIH, Iout = 0 mA, All Inputs = VIL and VIH,
VIL = 0 V and VIH 3.0 V, Cycle Time tAVAV min)
Output Low Voltage (IOL = + 8.0 mA)
Output High Voltage (IOH = – 4.0 mA)
ISB — 40 50 mA
VOL
0.4 V
VOH
2.4
—V
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol
Typ
Max Unit
Input Capacitance (All Pins Except DQ0 – DQ15)
Input/Output Capacitance (DQ0 – DQ15)
Cin
Cout
4
8
6 pF
10 pF
MCM62996
2
MOTOROLA FAST SRAM







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