Document
32 Bit RISC Microcontroller
TX03 Series
TMPM330FDFG/FYFG/FWFG
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TMPM330FDFG/FYFG/FWFG
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TMPM330FDFG/FYFG/FWFG
Introduction: Notes on the description of SFR (Special Function Register) under this specification
An SFR (Special Function Register) is a control register for periperal circuits (IP). The SFR addressses of IPs are described in the chapter on memory map, and the details of SFR are given in the chapter of each IP. Definition of SFR used in this specification is in accordance with the following rules.
a. SFR table of each IP as an example ・ SFR tables in each chapter of IP provides register names, addresses and brief descriptions. ・ All registers have a 32-bit unique address and the addresses of the registers are defined as follows, with some exceptions: "Base address + (Unique) address"
Control register
Register name
SAMCR
Base Address = 0x0000_0000 Address(Base+) 0x0004 0x000C
Note: SAMCR register address is 32 bits wide from the address 0x0000_0004 (Base Address(0x00000000) + unique address (0x0004)).
Note: The register shown above is an example for explanation purpose and not for demonstration purpose. This register does not exist in this microcontroller.
b. SFR(register) ・ Each register basically consists of a 32-bit register (some exceptions). ・ The description of each register provides bits, bit symbols, types, initial values after reset and functions.
TMPM330FDFG/FYFG/FWFG
1.2.2 SAMCR(Control register)
31
30
29
28
27
26
bit symbol
-
-
-
-
-
-
After reset
0
0
0
0
0
0
23
22
21
20
19
18
bit symbol
-
-
-
-
-
-
After reset
0
0
0
0
0
0
15
14
13
12
11
10
bit symbol
-
-
-
-
-
-
After reset
0
0
0
0
0
0
7
6
5
4
3
2
bit symbol
MODE
TDATA
After reset
0
0
0
1
0
0
Bit 31-10 9-7
6-0
Bit Symbol − MODE[2:0]
TDATA[6:0]
Type R R/W
W
"0" can be read.
Operation mode settings 000 : Sample mode 0 001 : Sample mode 1 010 : Sample mode 2 011 : Sample mode 3 The settings other than those above: Reserved
Transmitted data
Function
Note: The Type is divided into three as shown below.
25
24
-
-
0
0
17
16
-
-
0
0
9
8
MODE
0
0
1
0
0
0
R/W R W
READ WRITE READ WRITE
c. Data descriptopn
Meanings of symbols used in the SFR description are as shown below. ・ x:channel numbers/ports ・ n,m:bit numbers
d. Register descriptoption Registers are described as shown below. ・ Register name Exmaple: SAMCR="000" or SAMCR="000" indicates bit 2 to bit 0 in bit symbol mode (3bit width). ・ Register name [Bit] Example: SAMCR[9:7]="000" It indicates bit 9 to bit 7 of the register SAMCR (32 bit width).
TMPM330FDFG/FYFG/FWFG
Date 2010/04/26 2010/10/06 2023/07/31
Revision History
Revision 1 2
Comment First Release Contents Revised
3
Contents Revised
Table of Contents
Introduction: Notes on the description of SFR (Special Function Register) under this specification
TMPM330FDFG/FYFG/FWFG
1.1 Features......................................................................................................................................1 1.2 Block Diagram...........................................................................................................................4 1.3 Pin Layout (Top view)...............................................................................................................5 1.4 Pin names and Functions...........................................................................................................6
1.4.1 Sorted by Pin........................................................................................................................................................................6 1.4.2 Sorted by Port....................................................................................................................................................................12
1.5 Pin Numbers and Power Supply Pins......................................................................................18
2. Processor Core
2.1 Information on the processor core...........................................................................................19 2.2 Configurable Options...............................................................................................................19 2.3 Exceptions/ Interruptions...................................................................................................