Document
32 Bit RISC Microcontroller
TX03 Series
TMPM367FDXBG
Dear customers
Sep. 01, 2021
Toshiba Electronic Devices & Storage Corporation Toshiba Electronic Device Solutions Corporation
5801-1, Horikawatyou, Saiwai Ward, Kawasaki City, Kanagawa prefecture, 212-8520 Tel: +81-44-548-2200 Fax: +81-44-548-8965
Error correction for technical datasheet of Universal Asynchronous Receiver-Transmitter
Thank you for using Toshiba microcontrollers.
We have found the mistakes about occurring transmission interrupt timing of the Universal Asynchronous Receiver-Transmitter (UART and FUART) and the Universal Asynchronous Receiver-Transmitter Circuit with 50% duty mode (UART) in our technical datasheet and reference manual. We will inform you about the mistakes in this document.
We apologize for any inconvenience, but we ask that you review the content.
If you have any questions, please contact our sales representative.
1. Applicable products
TMPM342FYXBG TMPM343F10XBG TMPM343FDXBG TMPM366F20AFG TMPM366FWFG TMPM366FYFG TMPM366FDFG TMPM366FWXBG TMPM366FYXBG TMPM366FDXBG TMPM367FDFG TMPM367FDXBG TMPM368FDFG TMPM368FDXBG TMPM369FDFG TMPM369FDXBG TMPM36BF10FG TMPM36BFYFG TMPM381FWDFG TMPM381FWFG TMPM383FSEFG TMPM383FSUG TMPM383FWEFG TMPM383FWUG TMPM3V4FSEFG TMPM3V4FSUG TMPM3V4FWEFG TMPM3V4FWUG TMPM3V6FWDFG TMPM3V6FWFG
TMPM440FEXBG TMPM440F10XBG TMPM461F10FG TMPM461F15FG TMPM462F10FG TMPM462F15FG TMPM46BF10FG TMPM4G6FDFG TMPM4G6FEFG TMPM4G6F10FG TMPM4G7FDFG TMPM4G7FEFG TMPM4G7F10FG TMPM4G8FDFG TMPM4G8FDXBG TMPM4G8FEFG TMPM4G8FEXBG TMPM4G8F10FG TMPM4G8F10XBG TMPM4G8F15FG TMPM4G8F15XBG TMPM4G9FDFG TMPM4G9FDXBG TMPM4G9FEFG TMPM4G9FEXBG TMPM4G9F10FG TMPM4G9F10XBG TMPM4G9F15FG TMPM4G9F15XBG
TMPA900CMXBG TMPA901CMXBG TMPA910CRAXBG TMPA910CRBXBG TMPA911CRXBG TMPA912CMXBG TMPA913CHXBG
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2. Details
The timing of occurring transmission interrupt is shown as below. There is the mistake in the timing of occurring transmission interrupt when the transmission FIFO is not used only, and it will be corrected as below. There is no mistake in the transmission interrupt timing when using the transmission FIFO.
2.1. When the transmission FIFO is unused
Transmission interrupt occurs when a transmission data moves from the transmission buffer (the 1st level of transmission FIFO) to transmission shift register. (When the transmission buffer becomes empty.)
Transmission Shift Register
UTxTXD
Transmission interrupt occurs
Transmission FIFO 1st 2nd 3rd 4th
Transmission buffer
32nd
2.1.1. The timing of occurring transmission interrupt
The transmission interrupt when the transmission FIFO is not used occurs when the transmission buffer becomes empty because it notifies the timing of writing to the transmission buffer for the next data. The transmission interrupt is automatically cleared when the next data is written to the transmission buffer. Therefore, it is not necessary to clear the transmission interrupt by software when continuously transmitting data (set UARTxICR to "1").
When the transmission is terminated, the final transmission data is transferred to the shift register, and the final transmission interrupt occurs when the transmission buffer becomes empty. If the next data is not written to the transmission buffer, the transmission interrupt can be intentionally cleared by executing clear by software in the interrupt handler (set UARTxICR to "1").
If you execute the transmission interrupt clear by software during data transmission (set UARTxICR to "1"), the transmission interrupt does not occur if you write the data to the transmission buffer at the same time as the STOP bit is generated. In order to generate the transmission interrupt reliably, do not clear the transmission interrupt by software, write data to the transmission buffer during data transmission, or write the data to the transmission buffer while transmission is stopped (when UARTxFR= "0").
When transmitting data continuously, it is recommended to transfer the data by using the transmission FIFO in the next section.
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2.2. When transmission FIFO is used
Transmission interrupt occurs when transmission FIFO level matches with preset FIFO level which is specified by UARTxIFLS.
Transmission Shift Register
UTxTXD
Transmission FIFO 1st 2nd 3rd 4th
32nd Transmission buffer
Transmission interrupt occurs when transmission FIFO fill level matches with preset FIFO level
e.g.: UARTxIFLS= "000" 1/8 Full (4 bytes) setting
2.2.1. The timing of occurring transmission interrupt
When using the transmission FIFO, the transmission interrupt occurs when transmission FIFO level matches with preset FIFO level.
For example, in case of UARTxIFLS = "000" (1/8 full 4 bytes setting), the transmission interrupt occurs when the transmission FIFO level matches with 4th level.
The transmission interrupt is cleared when data whose FIFO level is above the specified FIFO level is stored in the transmission FIFO and occurs again when.