CD4724BMS

CD4724BMS December 1992 CMOS 8-Bit Addressable Latch Pinout CD4724BMS TOP VIEW Features High Voltage Type (20V Rating) Serial Data Input Active Parallel Output Storage Register Capability Master Clear Can Function as Demultiplexer Standardized Symmetrical Output Characteristics 100% Tested for Quiescent Current at 20V Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V 5V, 10V and 15V Parametric Ratings Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” A0 A1 A2 Q0 Q1 Q2 Q3 VSS 1 2 3 4 5 6 7 8 16 VDD 15 RESET 14 WRITE DISABLE 13 DATA 12 Q7 11 Q6 10 Q5 9 Q4 Functional Diagram WRITE DISABLE 14 13 4 5 6 8 LATCHES Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Applications Multi-line Decoders A/D Converters DATA 1 A0 A1 A2 2 3 DECODER 8 7 9 10 11 Description CD4724BMS 8-bit addressable latch is a serial-input, paralleloutput storage register that can perform a variety of functions. Data are inputted to a particular bit in the latch when that bit is addressed (by means of inputs A0, A1, A2) and when WRITE DISABLE is at a low level. When WRITE DISABLE is high, data entry is inhibited; however, all 8 outputs can be continuously read independent of WRITE DISABLE and address inputs. A master RESET input is available, which resets all bits to a...