8 Decoder. CDP1853 Datasheet

CDP1853 Decoder. Datasheet pdf. Equivalent


GE CDP1853
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Peripherals
CDP1853, CDP1853C
TERMINAL ASSIGNMENT
CLOCK A
NO
NI
our a
ouT I
ouT 2
OUT 3
Vss
I,..
I.
"12
"10
9
TOP VIEW
Voo
CLOCK B
NC.'
OUT4
OUT'
OUT 6
our 7
N-Bit 1 of 8 Decoder
Features:
• Provides direct control of up to
7 input and 7 output devices
• CHIP ENABLE (CE) allows easy
expansion for multi-level I/O systems
The RCA-CDP1853 and CDP1853C are 1 of 8 decoders
designed for use in general purpose microprocessor
systems. These devices, which are functionally identical,
are specifically designed for use as gated N-bit decoders
and interface directly with the 1800-series microprocessors
without additional components. The CDP1853 has a
recommended operating voltage range of 4 to 10.5 volts,
and the CDP1853C has a recommended operatinQ voltage
range of 4 to 6.5 volts.
When CHIP ENABLE (CE) is high, the selected output will
be true (high) from the trailing edge of CLOCK A (high-to-
low transition) to the trailing edge of CLOCK B (high-to-Iow
transition). All outputs will be low when the device is not
.,2..(>-
N2 14
I OF 8
DECODER
"-OUT 0
5 OUT I
6 OUT 2
I~ ~~~:
II OU15
10 OUT 6
9 OUT 7
CLOCK A -'-'--f',.....=c=:::a;~1
(TPM
CLOCK B 15
(TPB) ---" /"'~-____~__~_ _ _ _- '
Fig. 1 - CDPI853 functional diagram.
selected (CE=O) and during conditions of CLOCK A and
CLOCK B as shown in Fig. 2. The CDP1853 inputs NO, Nl,
N2, CLOCK A, and CLOCK B are connected to an 1800
series microprocessor outputs NO, Nl, N2, TPA, and TPB
respectively, when used to decode I/O commands as shown
in Fig. 5. The CHIP ENABLE (CE) input provides the
capability for multiple levels of decoding as shown in Fig. 6.
The CDP1853 can also be used as a general 1 of 8 decoder
for I/O and memory system applications as shown in Fig. 4.
The CDP1853 and CDP1853C are supplied in hermetic 16-
lead'dual-in-line ceramic (0 suffiX) and plastiC (E suffiX)
packages.
TRUTH TABLE
CE CLA CL B EN
10
0 On-l*
10 1 1
11 0 0
11 1 1
0X X 0
N2 N1 NO EN 0 1 2 3 4 5 6 7
0 0 0 1 10000000
0 0 1 1 0 10 0 00 0 0
0 1 0 1 00 100000
0 1 1 1 000 10000
1 0 0 1 0000 1000
1 0 1 1 00000 100
1 1 0 1 000000 10
1 1 1 1 0000000 1
X X X 0 00000000
*1 = High level 0 = Low level X = Don't care
On-1 = Enable remains In previous state.
III
File Number 1189
_______________________________________________________________ 383


CDP1853 Datasheet
Recommendation CDP1853 Datasheet
Part CDP1853
Description N-Bit 1 of 8 Decoder
Feature CDP1853; _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Peripherals CDP1853, CDP1853C TERMINAL ASS.
Manufacture GE
Datasheet
Download CDP1853 Datasheet




GE CDP1853
CMOS Peripherals - - - - - - - - - - - - - - - - - - - - - - - - -
CDP1853, CDP1853C
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY·VOLTAGE RANGE, (VDO)
(All voltage values referenced to VSS terminal
CDP1853 ............................................................ -0.5to+ll V
CDPI853C .. ......................................................... -0.6 to + 7 V
INPUT VOLTAGE RANGE, ALL INPUTS.. . .. . . . .................. -0.5 to VDD + 0.5 V
DC INPUT CURRENT, ANY ONE INPUT ...... .................................... ± 10 mpt
OPERATlNG·TEMPERATURE RANGE (TA):
°
CERAMIC PACKAGES (0 SUFFIX TYPES) .............................••. -55 to + 125oC
PLASTIC PACKAGES (E SUFFIX TYPES) .................................. -40to+85oC
STORAGE TEMPERATURE RANGE (T til) ......• • ..•••..................... -65 to + 160 C
LEAD TEMPERATURE (DURING SOLdERING):
°
At distance 1/16 ±1/32 inch (1.59±o.79 mm) from case for 10 s max•.............•....... +265 C
STATIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85°C. Except as noted
CHARACTER ISTIC
Qu iescent Device
Current,l L
Output Low Drive
(Sink) Current,
IOL
Output High Drive
(Source Current)
IOH
Output Voltage
Low· Level ..
VOL
Output V,oltage
High Level
V OH
Input Low Voltage
V IL
Input High Voltage
V IH
Input Leakage
Current liN
.Operating Current
1001
Input Capacitance
CIN
Output Capacitance
COUT
CONDITIONS
LIMITS
COP1853
CDP1853C UNITS
vo
(V)
VIN VDD
(V) (V) Min.
Typ.t Max.
Min. Typ.t Max.
- - 5-
- - 10 -
1 10 -
10 100 -
5 50
- - IJ.A
-0.4 0,5 5 1.6
-0.5 0,10 10 2.6
3.2 -
5.2 -
1.6 3.2
-
-
mA
- -4.6 0,5 5 ·1.15 ·2.3 - ·1.15 ·2.3
9.5 0,10 10 ·2.6 ·5.2
-
-
-
rnA
- 0,5 5 -
-- 0,10 10
0 0.1
0 0.1
-
-
0 0.1
--
- 0,5 5 4.9 5 - 4.9 5
- 0,10 10 9.9 10 - - -
-
-
V
0.5,4.5 -
1,9 -
5-
10 -
- 1.5 -
- 3-
0.5,4.5 -
1,9 -
5 3.5 - - 3.5
10 7 - - -
Any 0,5 5 - - ±1 -
Input 0,10 10 - - ±1 -
0,5 0,5
0,10 0,10
--
5
10
-
- 50 100
- 150 300
- 5 7.5
-
-
-
-
-
-
-
-
-
50
-
5
1.5
-
V
-
-
±1
- IJ.A
100
- IJ.A
7.5 pF
-- -
- 10 15 - 10 15 pF
t TYPical values are for TA= 25°C and nommal voltage.
• Operating current measured In a CDP1802 system at 2MHz with outputs floating.
.. IOL = IOH= llJ.A
384 _______________________________________________________________



GE CDP1853
CMOS Peripherals
CDP1853, CDP1853C
OPERATING CONDITIONS at T A = Full Package-Temperature Range. For maximum
reliability, operating conditions should be selected so that operation is always within
the following ranges:
LIMITS
CHARACTERISTIC
CDP1853 CDP1853C
UNITS
Supply· Voltage Range
Recommended Input Voltage Range
Min. Max. Min.
4 10.5 4
VSS VDD VSS
Max.
6.5
VDD
V
V
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = -40 to +85°C, V DD5%,
V IH = 0.7 V DD , V il = 0.3 VDD, t r, ~ = 20 ns, Cl = 100pF
CHARACTERISTIC
V DD
(V)
LIMITS
CDP1853
CDP1853C
UNITS
Typ. Max. Typ. Max.
Propagation Delay Time:
CE to Output, tEOH' tEOl
N to Outputs, tNo H' t NO l
Clock A to Output, tAO
Clock B to Output, tBo
5 175 275 175 275 ns
10 90 150 -
-
5 225 350 225 350 ns
10 120 200
-
-
5 200 300 200 300 ns
10 100 150
-
-
5 175 275 175 275 ns
10 90 150 -
-
Minimum Pulse Widths:
Clock A, tCACA
Clock B, t CBCB
5 50 75 50 75
10 25 50 -
-
5 50 75 50 75 ns
10 25 50 -
-
Note 1: Maximum limits of minimum characteristics are the values above which all devices
function.
Note 2: Typical values are for TA = 25°C and nominal voltages.
~CLOCK A
CACA--1
IAO~
'EO~""
.. - 'EO
C'~
OUTPUT~
01 CE TO OUTPUT (O-f) DELAY TIME
'NO---+-"~
~-t 'NO
N~'
~
OUTPUT~
b) N LINES TO OUTPUT (0-71 DELAY TIME
OUTPuT
=3'CBCB3-cl CLOCK A TO OUTPUT (0-7) DELAY TIME
CLOC< B
'BO
OUTPUT
d) CLOCK B TO OUTPUT (0-7) DELAY TIME
FIg 2 ~ PropagatIon delav tIme dIagrams.
TPA
OUTPUT
• OUTPUT ENABLED WHEN EN' HIGH
INTERNAL SIGNAL SHOWN FOR REFERENCE ONLY (SEE FIG I)
Fig. 3 - Tlmmg dIagram.
CHIP ENABLE
Voo
NO
NI
N2
CE
OUT I
Fig. 4 - N-blt decoder used as a 1 of 8
decoder.
..
_______________________________________________________________ 385





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