Output Ports. CDP1875C Datasheet

CDP1875C Ports. Datasheet pdf. Equivalent


GE CDP1875C
_____________________________________ CMOS Peripherals
CDP1872C, CDP1874C, CDP1875C
(51 22 VDD
010 21 017
000
20 007
01 I
19 016
DO I
012 -
18 006
17 oro
002 16 005
Dt3 ~ 8
15 014
003 ---
14 004
CLOCK
~~~
13 - CLR
Vss ---~___ I.T- C52
TOP vIE W
CDP1872C Input Port
TERMINAL ASSIGNMENT
High-Speed 8-Bit Input and Output Ports
Features:
• Parallel 8-bit input/output register with buffered outputs
• High-spead data-in to data-out:
85 ns (max.) at Vee = 5 V
• Flexible applications in microprocessor systems as
buffers and latches
• High order address-latch capability in CDP1800 series
microprocessor systems
• Output sink current = 5 mA (min.) at Vee = 5 V
• 3-state output - CDP1872C and CDP1874C
The RCA-COP1872C, COP1874C and COP1875C devices
are high-speed 8-bit parallel input and output ports designed
for use in the COP1800 microprocessor system and for
general use in other microprocessor systems. The
CDP1872C and COP1874C are 8-bit input ports; the
COP1875C is an 8-bit output port.
These devices have flexible capabilities as buffers and data
latches and are reset by CLR input when the data strobe is
not active.
The CDP1872C and CDP1874C are functionally identical
except for device selects. The CDP1872C has one active
low and one active high select; the COP1874C has two
active high device selects. These devices also feature 3-
state outputs when deselected. Data is strobed into the
register on the leading edge of the CLOCK and latched on
the trailing edge of the CLOCK.
The CDP1875C is an output port with data latched into the
registers when the device selects are active. There are two
active high and one active low selects. The output buffers
are enabled at all ti meso
..
These devices are supplied in 22-lead hermetic, dual-in-line
side-brazed ceramic packages (0 suffix) and in 22-lead
dual-in-line plastic package (E suffix).
CSI
010
DOD
01 I
001
012
002
013
003
CLOCK
VSS
22
21
20
4 19
5 18
17
16
15
14
10 13
" 12
TOP VIEW
VDD
017
007
016
006
015
005
014
004
eLR
CS2
92CS- 33011
CDP1874C Input Port
TERMINAL ASSIGNMENT
,--~
CSi ~I
22
010
2
21
000
3
OIl ~4
001 5
20
19
18
012 --.-J6
17
002 17
16
DI3~15
003 9
14
C53
10
13
Yss II
12
-
"'DO
017
007
016
006
015
005
014
004
CLR
C52
TOP VIEW
92CS-33010
CDP1875C Output Port
TERMINAL ASSIGNMENT
File Number 1255
________________________________________________ 425


CDP1875C Datasheet
Recommendation CDP1875C Datasheet
Part CDP1875C
Description High-Speed 8-Bit Input and Output Ports
Feature CDP1875C; _____________________________________ CMOS Peripherals CDP1872C, CDP1874C, CDP1875C (51 22 VDD 010.
Manufacture GE
Datasheet
Download CDP1875C Datasheet




GE CDP1875C
CMOS Peripherals _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CDP1872C, CDP1874C, CDP1875C
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (Voo) .................................................................................. -o.S to +7 V
(Voltage referenced to Vs. Terminal)
INPUT VOLTAGE RANGE, ALL INPUTS ...•...................................................................... -O.S to Voo +O.S V
DC INPUT CURRENT, ANY ONE INPUT ................................................................................... ±10 rnA
POWER DISSIPATION PER PACKAGE (Po).
For T. = -40° C to +60° C (PACKAGE TYPE E) ............................................................................ SOO mW
For T. = +60°C to +8SoC (PACKAGE TYPE E) .............................................. Derate Linearly at 12 mWI'C to 200 mW
For T. = -SsoC to +100'C (PACKAGE TYPE D) ........................................................................... SOO mW
For T. = +100'C to +12S'C (PACKAGE TYPE D) ............................................ Derate Linearly at 12 mW/'C to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR T. - FULL PACKAGE-TEMPERATURE RANGE (All Package Types) .................................................. 100 mW
OPERATING-TEMPERATURE RANGE (TA)'
PACKAGE TYPE D .............................................................................................-SS'C to +12S'C
PACKAGE TYPE E .............................................................................................. -40'C to +8S'C
STORAGE TEMPERATURE RANGE (T."') .......................................................................... -6S'C to +1S0'C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.S9 ± 0.79 mm) from case for 10 s max. ....................................................... +26S' C
RECOMMENDED OPERATING CONDITIONS at TA = -40°C to +85'C.
For maximum reliability, operating conditions should be selected so that operation Is always within the following ranges:
CHARACTERISTIC
DC Operating-Voltage Range
Input Voltage Range
LIMITS
ALL TYPES
4to 6.5
Vss to Voo
UNITS
V
STATIC ELECTRICAL CHARACTERISTICS at TA = -40°C to +85°C, Voo ± 5%, except as noted
CHARACTERISTIC
Quiescent Device Current
Output Low Drive (Sink) Current
Output High Drive (Source) Current
Output Voltage Low-Level *
Output Voltage High-Level *
Input Low Voltage
Input High Voltage
Input Leakage Current
3-State Output Leakage Current #
Input CapaCitance
Output Capacitance #
• Typical values are for TA = 25°C and Voo ±5%.
* 10L = IOH = 1 /lA.
# For CDP1872C and CDP1874C only.
100
10L
10H
VOL
VOH
V,L
V,H
I,N
lOUT
C'N
COUT
TEST CONDITIONS
Vo V,N
(V) (V)
-
0.4
4.6
-
-
0.5,4.5
0.5,4.5
-
0,5
-
0,5
0,5
0,5
0,5
0,5
-
-
0,5
0,5
-
--
Voo
(V)
5
5
5
5
5
5
5
5
5
-
-
LIMITS
ALL TYPES
UNITS
MIN. TYP•• MAX.
- 25 50 /lA
5 10 -
rnA
-4 -7 -
- a 0.1
4.9 5 -
V
- - 1.5
3.5 -
-
- - ±1
-
-
/lA
±5
- 15 -
pF
- 15 -
426 ___________________________________________________________



GE CDP1875C
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Peripherals
CSi _..r------.
CS2 / - - - - - - - - - - ,
DI--------i
CLOCK - - t - - - - - - - i
CDP1872C, CDP1874C, CDP1875C
CSI
CS2
DI------~D
DO
CLOCK - - t - - - - - - - i
DO
92CS-33008
Fig. 1 - Equivalent logic diagram (1 of 8 latches shown)
for CDP1872C.
DI
es;
CS2
CS3
92cs-nOO9
Fig. 2 - Equivalent logic diagram (1 of 8 latches shown)
for CDP1874C.
DO
92CS~33007
Fig. 3 - Equivalent logic diagram (1 of 8 latches shown)
for CDP1875C.
= = = =DYNAMIC ELECTRICAL CHARACTERISTICS at TA 25°C, Yoo 5 Y, t" tt 10 ns, YIH 0.7 Yoo,
= =Yll 0.3 Yoo, Cl 150 pF
CHARACTERISTIC
LIMITS
CDP1872C
CDP1874C
T Y P• •
MAX·t
UNITS
Input Port (Fig. 4)
Output E: '1ble
tEN 45
90
Output Disable
tOIS 45
90
Clock to Data Out
tOLO 45
90
Clear to Output
Data In to Data Out
tCRO 80
160
tOIO 50
85
ns
Minimum Data Setup Time
tosu 10
30
Data Hold Time
tOH 10
30
Minimum Clock Pulse Width
tel 30
60
Minimum Clear Pulse Width
tCR 30
60
=• Typical values are for TA 25° C and Voo ±5%.
~, - - - - - - - - - - - - - - - - - - - - - - - - ,~C(C§DiP'CI8S722CI
=t Maximum values are for TA 85° C and Voo ±5%.
(CCSDIP' IC87S42CI '
i :fftjlDSU IDH
~
I
CLOCK
DATA IN
I- - - T - - - -
_-----JII ~'--:I-_
-I -,---O~'--I-IlcL-~-i -
I
pDATA BUS
(HIGH Z)
rIEN
\
:
tCLol
~tDIS~
'"----;---,.JJ ~ 1"1....-----CLR
M
92CM'33(106
_ _ _ _ _ _ _F_ig. _4 - T_imin_g w_ave_form_s fo_r C_DP1_872_C an_d C_DP1_874_C (_Inpu_t-po_rt ty_pes_). _ _ _ _ _ _ 427







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)