HCMOS Microcomputers. CDP68HC05C4 Datasheet

CDP68HC05C4 Microcomputers. Datasheet pdf. Equivalent


GE CDP68HC05C4
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 6805-Series Microprocessors and Microcomputers
CDP68HCOSC4, CDP68HCOSC8
HCMOS Microcomputers
SECTION 1
INTRODUCTION
1.1 GENERAL
The CDP68HC05C4 HCMOS Microcomputer is a member of the CDP68HC05 Family of
low-cost single-chip microcomputers. This 8-bit microcomputer contains an on-chip
oscillator, CPU, RAM, ROM, 1/0, two serial interface systems, and timer. The fully static
design allows operation at frequencies down to dc, further reducing its already low-power
consumption.
The CDP68HC05C8 Microcomputer (MCU) device is similar to the CDP68HC05C4 MCU
with one exception. This exception incorporates 3584 additional bytes of user ROM for a
total of 7744 bytes of on-chip user ROM. All information on the CDP68HC05C4 MCU
applies to the CDP68HC05C8 MCU with the exception of the memory description.
1.2 FEATURES
The following are some of the hardware and software highlights of these HCMOS
Microcomputers.
HARDWARE FEATURES
• HCMOS Technology
• 8-Bit Architecture
• Power-Saving Stop and Wait Modes
• Fully Static Operation
• 176 Bytes of On-Chip RAM
• 4160 Bytes of On-Chip ROM (CDP68HC05C4)
7744 Bytes of On-Chip ROM (CDP68HC05C8)
• 24 Bidirectional 1/0 Lines
• 2.1-MHz Internal Operating Frequency at 5 Volts; 1 MHz at 3 Volts
• Internal 16-Bit Timer Similar to MC6801 Timer
• Serial Communications Interface System
• Serial Peripheral Interface System
• Self-Check Mode
• External, Timer, Serial Communications Interface, and Serial Peripheral Interface
Interrupts
• Master Reset and Power-On Reset
• Single 3- to 6-Volt Supply (2-V Data Retention Mode)
• On-Chip Oscillator with RC or Crystal Mask Options
• 40-Pin Dual-In-Line Package
• 44-Lead Plastic Chip Carrie~,Also Available
TSM·203A
__________________________________________ 111
3


CDP68HC05C4 Datasheet
Recommendation CDP68HC05C4 Datasheet
Part CDP68HC05C4
Description HCMOS Microcomputers
Feature CDP68HC05C4; _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 6805-Series Microprocessors and Microcomputers CDP68HCOSC4, CDP68HCOSC.
Manufacture GE
Datasheet
Download CDP68HC05C4 Datasheet




GE CDP68HC05C4
6805~Series Microprocessors and Microcomputers _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CDP68HC05C4, CDP68HC05C8
SOFTWARE FEATURES
• Similar to MC6800
• 8 x 8 Unsigned Multiply Instruction
• Efficient Use of Program Space
• Versatile Interrupt Handling
• True Bit Manipulation
• Addressing Modes with Indexed Addressing for Tables
• Efficient Instruction Set
• Memory Mapped I/O
• Two Power-Saving Standby Modes
• Upward Software Compatible with the CDP6805 CMOS Family
Port
A
1/0
lmes
PAO
PAl
PA2
PA3
PA4
PA5
PA6
PA7
Port
B
1/0
lines
PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7
TCMP
OSC1 OSC2
Internal
Data
0"
Reg
Data
0"
Reg
Accumulator
8A
Index
Register
8X
Condition
Code
5 Register CC
Stack
POinter
6S
Program
Counter
5 High PCH
Program
Counter
8 low PCl
CPU
Control
CPU
AlU
240 x 8
Self-Check
ROM
"7744 bytes of ROM
for CDP68HC05C8
Figure '-1. Microcomputer Block Diagram
1 RESET
2 IRQ
Data
0"
Reg
Port
C
Reg
Peo
PCl Port
PC2 C
PC3 1/0
PC4 lines
PC5
PC6
PC7
Port 0
SCI
System
SPI
System
Baud Rate
Generator
PD7
RDI !POOl
TOO IPDlI
MISO IPD21
MOSIIPD31
SCK IPD41
SS IPD51
Internal
Processor
Clock
112 ________________________________________



GE CDP68HC05C4
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 6805-Serles Microprocessors and Microcomputers
CDP68HC05C4, CDP68HC05C8
SECTION 2
FUNCTIONAL PIN DESCRIPTION, INPUT/OUTPUT PROGRAMMING,
MEMORY, CPU REGISTERS, AND SELF-CHECK
This section provides a description of the functional pins, input/output programming, memory,
CPU registers, and self-check.
2.1 FUNCTIONAL PIN DESCRIPTION
2.1.1 VDD and VSS
Power is supplied to the MCU using these two pins. VOO is power and VSS. is ground.
2.1.2 IRQ (Maskable Interrupt Requestt
IRQ is a programmable option which provides two different choices of interrupt triggering sensi-
tivity. These options are: 1) negative edge-sensitive triggering only, or 2) both negative edge-
sensitive and level-sensitive triggering. In the latter case, either type of input to the IRQ pin will pro-
duce the interrupt. The MCU completes the current instruction before it responds to the interrupt
request. When the iRO pin goes low for at least on tILlH, a logic one is latched internally to signify
an interrupt has been requested. When the MCU completes its current instruction, the interrupt
latch is tested. If the interrupt latch contains a logic one, and the interrupt mask bit (I bit) in the con-
dition code register is clear, the MCU then begins the interrupt sequence.
If the option is selected to include level-sensitive triggering, then the i'RQ input requires an external
resistor to VOO for "wire-OR" operation. See INTERRUPTS in Section 3 for more detail concerning
interrupts.
2.1.3 R'Em
The R"E'SE'i' input is not required for startup but can be used to reset the MCU internal state and pro-
vide an orderly software startup procedure. Refer to RESETS in Section 3 for a detailed description.
2.1.4 TCAP
The TCAP input controls the input capture feature for the on-chip programmable timer system.
Refer to INPUT CAPTURE REGISTER in Section 4 for additional information.
2.1.5 TCMP
The TCMP pin (35) provides an output for the output compare feature of the on-chip timer system.
Refer to OUTPUT COMPARE REGISTER in Section 4 for additional information.
_______________________________________________________________ 113





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